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參數(shù)資料
| 型號： | SAA6713H |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | XGA dual input flat panel controller |
| 中文描述： | 雙輸入的XGA液晶控制器 |
| 文件頁數(shù)： | 41/103頁 |
| 文件大?。?/td> | 521K |
| 代理商： | SAA6713H |
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2004 Apr 05
41
Philips Semiconductors
Product specification
XGA dual input flat panel controller
SAA6713H
7.4.1
C
LOCK SIGNALS
7.4.1.1
System clock
The system clock is applied to pin CLK and is used to drive
the internal control structures and block configuration, and
serves as input for the panel clock PLL. The maximum
clock rate is 50 MHz.
The system clock is directly taken from pin CLK if clk_div4
is set to logic 0; otherwise the system clock is derived from
the clock signal at pin CLK additionally divided by 4 as
shown in Table 18.
Table 18
System clock switching modes
7.4.1.2
Back-end clock
The back-end clock is the pixel clock used in data
processing behind the decoupling FIFO. Possible clock
rates lie between 5 and 100 MHz in case of single pixel
panel output, but it is identical with the panel clock; if using
double pixel mode it equals twice the panel clock.
The clock signal is generated by the panel clock PLL
based on the system clock if bclk_in_en is set to logic 0;
otherwise the signal applied externally to pin CLK is used
as system clock (see Table 19).
Table 19
Back-end clock switching modes
7.4.1.3
Front-end clock
The front-end clock is the pixel clock of the input section
and is generated by the line PLL in case of analog RGB
input or provided by the DVI data stream in case of DVI
input. The front-end clock rate can be up to 110 MHz.
Either the DVI clock or the line PLL generated clock signal
(for analog input) is used depending on the selected video
source. In both cases pin VCLK is switched as output for
the used clock signal.
An externally generated clock signal can also be
connected to pin VCLK if vclk_in_en is set to logic 1.
Alternatively, the back-end clock can be selected as
front-end clock, which is particularly needed if the picture
generator is used without an external clock source.
Front-end clock modes are shown in Table 20.
Table 20
Front-end clock switching modes; note 1
Note
1.
X = don’t care.
7.4.1.4
Configuration clock
The internal configuration clock is driving the configuration
parameters section of all modules. It is usually running at
half the back-end clock frequency. If somehow the
back-end clock is not usable for the configuration, the
systemclockcould beused to drivethe configurationclock
instead. The selection of the configuration clock source
could either be done automatically monitoring the
back-end clock or forced manually if this is desired. For
power saving issues the configuration clock is
powered-down during inactive periods when no data is
received or requested via the I
2
C-bus interface.
See Table 21 for configuration clock switching options.
Table 21
Configuration clock switching modes
clk_div4
SYSTEM
CLOCK
DESCRIPTION
0
1
CLK
1
4
CLK
direct input
divided by 4
bclk_in_en
BACK-END
CLOCK
DESCRIPTION
1
0
CLK
external clock
internal clock generation
PLL clock
frontend
_bclk
dvi_
select
vclk
_in_
en
FRONT-END
CLOCK
DESCRIPTION
1
X
X
back-end
clock
DVI clock
VCLK
initialization
0
0
1
0
X
1
DVI input
external clock
generation
internal clock
generation
0
0
0
line PLL
clock
cfgclk_select
CONFIGURATION
CLOCK
DESCRIPTION
0
half back-end clock
application
(stable back-end
clock)
initialization
1
CLK
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