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參數(shù)資料
| 型號： | S1C88409D |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 8.8 MHz, MICROCONTROLLER, UUC108 |
| 封裝： | DIE-108 |
| 文件頁數(shù)： | 65/250頁 |
| 文件大?。?/td> | 1877K |
| 代理商： | S1C88409D |
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S1C88409 TECHNICAL MANUAL
EPSON
147
CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface)
TXTRG: Transmission trigger/status
(00FF41HD1)
This bit is used as the transmission start trigger
and the operation status indicator (transmission/
stop status).
When "1" is read: During transmission
When "0" is read: During stop
When "1" is written: Transmission trigger
When "0" is written: Invalid
TXTRG is the transmission control bits (trigger/
status). Transmission starts when "1" is written to
TXTRG after writing the transmission data.
TXTRG can be read as the status. When it is "1", it
indicates transmission, and "0" indicates stoppage.
At initial reset, TXTRG is set to "0" (during stop).
RXEN: Receiving enable register (00FF41HD2)
Sets the serial interface to the receiving authorize
status.
When "1" is written: Receiving is enabled
When "0" is written: Receiving is disabled
Reading: Valid
The RXEN register is the receiving enable register.
When "1" is written to the register, the serial
interface shifts to a receiving authorize status.
When "0" is written, it shifts to a receiving dis-
abling status.
Set the RXEN register to "0" when setting the
transfer mode.
At initial reset, the RXEN is set to "0" (receiving is
disabled).
RXTRG: Receiving trigger/status (00FF41HD3)
This bit is used as the receiving start trigger, ready
to receive and the operation status indicator
(receiving/stop status).
When "1" is read: During receiving
When "0" is read: During stop
When "1" is written: Receiving trigger
/Ready to receive
When "0" is written: Invalid
RXTRG is the receiving control bits (trigger/
status).
In the clock synchronous mode, RXTRG is used as
a trigger to start receiving.
When received data has been read and the prepa-
ration for the next data receiving is completed,
write "1" in RXTRG to start receiving.
In the asynchronous mode, RXTRG is used to
prepare for the next data receiving. After reading
the received data from the receive data buffer,
write "1" in RXTRG to signify that the receive data
buffer is empty. If "1" is not written in RXTRG, the
overrun error flag OER will be set to "1" when the
next receiving is completed. (An overrun error will
be generated when the next receiving is completed
between reading the previous received data and
the writing of "1" to RXTRG.)
RXTRG can also be read as a status. When it is "1",
it indicates receiving, and "0" indicates stoppage.
This function is the same in both the clock syn-
chronous mode and the asynchronous mode.
At initial reset, RXTRG is set to "0" (during stop).
TRXD0–TRXD7: Transmit/receive data register
(00FF42H)
The TRXD register is the transmit/receive data
register for the serial interface.
During transmission
Write a transmission data to this register.
When "1" is written: HIGH level
When "0" is written: LOW level
Write the transmitting data prior to start transmis-
sion.
When transmitting data continuously, following
data should be written after the transmit comple-
tion interrupt occurs.
In the 7-bit asynchronous mode, TRXD7 is invalid.
The data written in this register is converted into
serial data, and output from the SOUT terminal as
the bit set to "1" is a high (VDD) level and the bit set
to "0" is a low (VSS) level.
During receiving
Received data can be read from this register.
When "1" is read: HIGH level
When "0" is read: LOW level
The data in the receive data buffer can be read.
Received data should be read after the receive
completion interrupt occurs.
In the asynchronous mode, the received data can
be read even while the next data is being received
because the receive data buffer is provided
separately from the shift register. (The buffer
function is not used in the clock synchronous
mode.)
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