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參數(shù)資料
| 型號(hào)： | S1C88409D |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 8.8 MHz, MICROCONTROLLER, UUC108 |
| 封裝： | DIE-108 |
| 文件頁數(shù)： | 116/250頁 |
| 文件大?。?/td> | 1877K |
| 代理商： | S1C88409D |
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192
EPSON
S1C88409 TECHNICAL MANUAL
CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and Standby Mode)
5.20.4 Interrupt factor flag
The interrupt factor flag is set to "1" when the
corresponding interrupt factor generates.
By reading the interrupt factor flag, it is possible to
confirm the interrupt factor that has been gener-
ated.
Interrupt factor flag that has been set to "1" is reset
to "0" by writing "1".
At initial reset, all the interrupt factor flags are
reset to "0".
Note: When the RETE instruction is executed
without resetting the interrupt factor flag
after an interrupt has been generated, the
same interrupt is generated again. There-
fore, the interrupt factor flag must be reset
(writing "1") in the interrupt handler routine.
5.20.5 Interrupt enable register
The interrupt enable registers corresponding to all
interrupt factor flags are provided to enable/
disable the interrupt requests to the CPU.
When "1" is written to the interrupt enable register,
the interrupt request is enabled and when "0" is
written, it is disabled. This register can also be
read, thus making it possible to confirm the setting
status.
At initial reset, all the interrupt enable registers are
set to "0" and all the interrupts except for NMI are
disabled.
5.20.6 Interrupt priority register and
interrupt priority level
Each interrupt system provides the interrupt
priority register shown in Table 5.20.3.1. By using
the interrupt priority register, the priority of each
interrupt can be changed so that the CPU can
process interrupt in order of priority. Conse-
quently, it is possible to make a multiple interrupt
system that meets the demand of the application.
The priority level of each interrupt system can be
optionally set to four levels (0 to 3) by the interrupt
priority register. However, when two or more
systems are set to the same priority level, they are
processed according to the default priority level.
Table 5.20.6.1 Setting of interrupt priority level
P 1
1
0
Interrupt priority level
Level 3
Level 2
Level 1
Level 0
P 0
1
0
1
0
(IRQ3)
(IRQ2)
(IRQ1)
(None)
**
At initial reset, all the interrupt priority registers
are set to "0" and all interrupts are set to level 0.
Furthermore, the priorities inside of each system
have been previously decided and they cannot be
changed.
The CPU can mask each interrupt by setting the
interrupt flags (I0 and I1). The relation between the
interrupt priority level of each system and inter-
rupt flags is shown in Table 5.20.6.2. The CPU
accepts only interrupts set in a higher level than
the interrupt flag setting.
The priority level of NMI (watchdog timer) is set
in level 4, so it is always accepted regardless of the
interrupt flag setting.
Table 5.20.6.2 Interrupt mask setting for CPU
I1
1
0
Acceptable interrupt
Level 4 (NMI)
Level 4, Level 3 (IRQ3)
Level 4, Level 3, Level 2 (IRQ2)
Level 4, Level 3, Level 2, Level 1 (IRQ1)
I0
1
0
1
0
After an interrupt is accepted, the interrupt flags
are changed to the same level of the interrupt
accepted as shown in Table 5.20.6.3 in order to
mask interrupt requests with the same priority
level or less. However, it is set to level 3 after an
NMI is accepted.
Table 5.20.6.3 Interrupt flags after
acceptance of interrupt
I1
1
0
Accepted interrupt priority level
Level 4
Level 3
Level 2
Level 1
I0
1
0
1
(NMI)
(IRQ3)
(IRQ2)
(IRQ1)
The interrupt flags changed are returned to the
previous value at return from the interrupt
handler routine.
Multiple interrupts up to 3 levels can be controlled
by only setting the interrupt priority registers.
Multiple interrupts exceeding 3 levels can be realized
by rewriting the interrupt flags and interrupt enable
register in the interrupt handler routine.
Note: Be aware if the interrupt flags are rewritten
(set to lower priority) prior to resetting the
interrupt factor flag after an interrupt is
generated, the same interrupt will be
generated again.
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