參數(shù)資料
型號(hào)： S1C88409D
元件分類(lèi)： 微控制器/微處理器
英文描述： 8-BIT, MROM, 8.8 MHz, MICROCONTROLLER, UUC108
封裝： DIE-108
文件頁(yè)數(shù)： 60/250頁(yè)
文件大?。?/td> 1877K
代理商： S1C88409D
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142
EPSON
S1C88409 TECHNICAL MANUAL
CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface)
Clock synchronous slave mode
This mode uses a clock input from the SCLK
terminal (output from the master device) as the
synchronous clock SCLK.
(1) Transmission timing in clock synchronous slave mode
Figure 5.14.9.3 shows the transmission timing
in clock synchronous slave mode.
After writing "1" to the TXTRG bit each bit of
transmission data is output from the SOUT
terminal at the falling edge of the synchronous
clock input from the SCLK terminal. When the
last bit is output, a transmit completion
interrupt is generated at the rising edge of the
synchronous clock.
Note: Do not write data to TXTRG, RXTRG and
the TRXD register during transmission
(while reading of TXTRG is "1").
(2) Receiving timing in clock synchronous slave mode
Figure 5.14.9.4 shows the receiving timing in
clock synchronous slave mode.
After writing "1" to the RXTRG bit, the status of
the SIN terminal is input at each rising edge of
the synchronous clock input from the SCLK
terminal. When the last bit is input, a receive
completion interrupt is generated simultaneously.
After the interrupt is generated, the received data
can be read from the TRXD register.
When a parity error or a framing error (stop bit =
"0") occurs, the error interrupt is generated at the
same time as the receive completion interrupt. An
overrun error occurs when the next data is
received before reading the previous received
data. In this case, the interrupt generation timing
is the same as other interrupts.
Note: Do not write data to TXTRG, RXTRG and
the TRXD register during receiving (while
reading of RXTRG is "1").
(3) Transmit/receive ready (SRDY) signal
When the serial interface is used in the clock
synchronous slave mode, it can output the
SRDY signal that indicates whether the serial
interface is ready to transmit/receive or not.
The SRDY signal is output from the SRDY
terminal as "0" (low level) when the serial
interface is in ready status (ready to transmit/
receive) and as "1" (high level) when it is in
busy status (during transmission/receiving).
The SRDY signal changes from "1" to "0"
immediately after writing "1" to TXTRG or
RXTRG, and returns from "0" to "1" when the
first synchronous clock is input (at rising edge).
(See Figure 5.14.9.3, Figure 5.14.9.4.)
Fig. 5.14.9.3 Transmission timing (clock synchronous slave mode)
Fig. 5.14.9.4 Receiving timing (clock synchronous slave mode)
TXEN
TXTRG (WR)
SCLK
SOUT
TXTRG (RD)
SRDY
Transmit completion
interrupt generation
D0
D1
D2
D3
D4
D5
D6
D7
RXEN
RXTRG (WR)
SCLK
SIN
TRXD (RD)
RXTRG (RD)
SRDY
Receive completion
interrupt generation
Received data
D0
D1
D2
D3
D4
D5
D6
D7
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