
S1C88409 TECHNICAL MANUAL
EPSON
73
CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (Input Ports)
K00D–K07D: K0 input port data (00FFC3H)
K10D–K13D: K1 input port data (00FFC4HD0–D3)
Input data of the input port terminals can be read
out.
When "1" is read: HIGH level
When "0" is read: LOW level
Writing: Invalid
The terminal voltage of each of the input ports
K00–K07 and K10–K13 can be directly read as
either a "1" when the terminal is high (VDD) level
or a "0" when the terminal is low (VSS) level.
These bits are dedicated for reading, so writing
cannot be done.
SIK00–SIK07: K0 port interrupt selection
register (00FFC0H)
Sets the interrupt generation condition (enables/
disables interrupt) for the K0 input port.
When "1" is written: Interrupt is enabled
When "0" is written: Interrupt is disabled
Reading: Valid
SIK0 is the interrupt selection register corresponding
to the input port K0. An interrupt of the port in
which the SIK0 bit is set to "1" is enabled, and the
others in which the SIK0 bit is set to "0" are disabled.
Change of the input terminal in which the inter-
rupt is disabled does not affect the interrupt
generation.
At initial reset, the SIK0 register is set to "0"
(interrupt is disabled).
The K10–K13 input port has no interrupt selection
register because the port can generate interrupts in
bit units.
KCP00–KCP07: K0 port input comparison
register (00FFC1H)
KCP10–KCP13: K1 port input comparison
register (00FFC2HD0–D3)
Sets the interrupt generation condition (interrupt
generation timing) for the K0 or K1 input port.
When "1" is written: Falling edge
When "0" is written: Rising edge
Reading: Valid
KCP is the input comparison register correspond-
ing to each input port. An interrupt of the port in
which the KCP bit is set to "1" is generated at the
falling edge of the input and an interrupt in which
the KCP bit is set to "0" is generated at the rising
edge.
At initial reset, the KCP register is set to "1" (falling
edge).
PK00, PK01: K0 input interrupt priority register
(00FF20HD4, D5)
PK10, PK11: K1 input interrupt priority register
(00FF20HD6, D7)
Sets the input interrupt priority level.
PK0 and PK1 are the interrupt priority registers
corresponding to the K0, K1 input interrupts.
Table 5.6.4.2 shows the interrupt priority level
which can be set by this register.
Table 5.6.4.2 Interrupt priority level settings
PK11
PK01
1
0
Interrupt priority level
Level 3
Level 2
Level 1
Level 0
PK10
PK00
1
0
1
0
(IRQ3)
(IRQ2)
(IRQ1)
(None)
At initial reset, the PK register is set to "0" (level 0).
EK0: K0 input interrupt enable register
(00FF23HD3)
EK10–EK13: K1 input interrupt enable register
(00FF23HD4–D7)
Enables or disables the interrupt generation to the
CPU.
When "1" is written: Interrupt is enabled
When "0" is written: Interrupt is disabled
Reading: Valid
EK0 is the interrupt enable register corresponding
to eight bits of the K0 port and EK10–EK13
correspond to each bit of the K10–K13 ports.
An interrupt of the port in which the EK register is
set to "1" is enabled, and the others in which the
EK register is set to "0" are disabled.
At initial reset, the EK register is set to "0" (inter-
rupt is disabled).
FK0: K0 input interrupt factor flag
(00FF27HD3)
FK10–FK13: K1 input interrupt factor flag
(00FF27HD4–D7)
Indicates the generation of input interrupt factor.
When "1" is read: Int. factor has generated
When "0" is read: Int. factor has not generated
When "1" is written: Factor flag is reset
When "0" is written: Invalid
FK0 is the interrupt factor flag corresponding to
eight bits of the K0 port and FK10–FK13 corre-
spond to each bit of the K10–K13 ports.
The interrupt factor flag is set to "1" when the
interrupt generation condition is met.