參數(shù)資料
型號(hào)： S1C88409D
元件分類(lèi)： 微控制器/微處理器
英文描述： 8-BIT, MROM, 8.8 MHz, MICROCONTROLLER, UUC108
封裝： DIE-108
文件頁(yè)數(shù)： 208/250頁(yè)
文件大?。?/td> 1877K
代理商： S1C88409D
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50
EPSON
S1C88409 TECHNICAL MANUAL
CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (System Controller and Bus Control)
BSMD0, BSMD1: Bus mode selection register
(00FF00HD6, D7)
Sets the bus mode as shown in Table 5.2.4.2.
Table 5.2.4.2 Bus mode settings
1
0
Expanded 4M maximum mode
Expanded 4M minimum mode
Expanded 64K mode
Single chip mode (MCU)
Optional setting of one of the expanded
mode (MPU)
Bus mode
Setting value
BSMD1
1
0
1
0
BSMD0
The single chip mode can be set only when the
S1C88409 is used in the MCU mode.
When using the external MPU interface, only the
single chip mode can be set.
In the MPU mode, the single chip mode cannot be
set since the MPU mode does not use the internal
ROM.
When using the S1C88409 in the MPU mode, it is
necessary to select the bus mode set at initial reset
(and when the BSMD register is set to "0") by mask
option from the three types of expanded modes:
expanded 64K mode, expanded 4M minimum
mode and expanded 4M maximum mode. Select
the expanded 4M maximum mode, when the MPU
mode is not used.
At initial reset, the BSMD register is set to "0"
(single chip mode in the MCU mode or an ex-
panded mode selected by mask option in the MPU
mode).
Note: After initial reset, all the interrupts including
NMI are masked until the appropriate
values are written to the I/O memory
addresses "00FF00H" and "00FF01H" to
prevent malfunctions that may occur before
setting the system configuration. Therefore,
write data to the addresses in the initial
routine even though operating the
S1C88409 in the initial settings (single chip
mode). Furthermore, set the stack pointer
SP prior to writing so that interrupt process-
ing will operate normally.
CEMD0, CEMD1: Expanded 64K chip enable
mode selection register (00FF00HD4, D5)
Sets the CE signal address range (valid only in the
expanded 64K mode).
Set this register according to the external memory
chip size as shown in Table 5.2.4.3.
Table 5.2.4.3 CE signal settings
CEMD1
1
0
CEMD0
1
0
1
0
Address
range
64K bytes
32K bytes
16K bytes
8K bytes
MCU mode
Invalid
CE0
CE0, CE1
CE0–CE2
Usable terminals
MPU mode
CE0
CE0, CE1
CE0–CE2
This setting is invalid for modes other than the
expanded 64K mode.
At initial reset, the CEMD register is set to "11B".
However, since "11B" is invalid in the MCU mode,
set it to another value.
CE0–CE2: CE signal output enable register
(00FF00HD0–D2)
Sets the CE output terminals to be used.
When "1" is written: CE output enabled
When "0" is written: CE output disabled
Reading: Valid
Writing "1" to the CE0–CE2 register enables the
corresponding CE signal to output.
Writing "0" to the register disables the CE signal to
output, and the terminal functions as the output
port (R30–R32).
At initial reset, the CE registers are all set to "1".
WT0, WT1: WAIT state control register
(00FF01HD4, D5)
Controls the WAIT state insertion.
Table 5.2.4.4 shows the register setting and the
number of WAIT states inserted.
Table 5.2.4.4 WAIT state settings
Number of inserted states
12
8
4
No wait
WT1
1
0
WT0
1
0
1
0
The length of one state is 1/2 a cycle of the clock.
At initial reset, the WT register is set to "0" (no wait).
5.2.5 Programming note
After initial reset, all the interrupts including NMI
are masked until the appropriate values are
written to the I/O memory addresses "00FF00H"
and "00FF01H" to prevent malfunctions that may
occur before setting the system configuration.
Therefore, write data to the addresses in the initial
routine even though the initial settings are used.
Furthermore, set the stack pointer SP prior to
writing so that interrupt processing will operate
normally.
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