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EPSON
S1C88409 TECHNICAL MANUAL
CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and Standby Mode)
Table 5.20.8.1(c) Interrupt control bits
Address
Function
R/W
Init
0
1
Comment
Name
Bit
00FFC0
K07 interrupt selection register
K06 interrupt selection register
K05 interrupt selection register
K04 interrupt selection register
K03 interrupt selection register
K02 interrupt selection register
K01 interrupt selection register
K00 interrupt selection register
R/W
0
Interrupt
is disabled
Interrupt
is enabled
SIK07
SIK06
SIK05
SIK04
SIK03
SIK02
SIK01
SIK00
D7
D6
D5
D4
D3
D2
D1
D0
00FFC1
K07 input comparison register
K06 input comparison register
K05 input comparison register
K04 input comparison register
K03 input comparison register
K02 input comparison register
K01 input comparison register
K00 input comparison register
R/W
1
Rising edge
generates
interrupt
Falling edge
generates
interrupt
KCP07
KCP06
KCP05
KCP04
KCP03
KCP02
KCP01
KCP00
D7
D6
D5
D4
D3
D2
D1
D0
00FFC2
–
K13 input comparison register
K12 input comparison register
K11 input comparison register
K10 input comparison register
–
R/W
–
1
–
Rising edge
generates
interrupt
–
Falling edge
generates
interrupt
"0" when being read
–
KCP13
KCP12
KCP11
KCP10
D7
D6
D5
D4
D3
D2
D1
D0
Refer to the explanations on the respective peripheral
circuits for the setting contents and control for each
bit.
5.20.9 Programming notes
(1) When the RETE instruction is executed without
resetting the interrupt factor flag after an
interrupt has been generated, the same inter-
rupt is generated again. Therefore, the inter-
rupt factor flag must be reset (writing "1") in
the interrupt handler routine.
(2) Be aware if the interrupt flags (I0, I1) are
rewritten (set to lower priority) prior to
resetting the interrupt factor flag after an
interrupt is generated, the same interrupt will
be generated again.
(3) An exception processing vector is fixed at 2
bytes, so it cannot specify a branch destination
bank address. Therefore, to branch from two or
more banks to a common exception handler
routine, the top portion of the exception
handler routine must be described within the
common area (000000H–007FFFH).