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參數(shù)資料
| 型號： | S1C88409D |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 8.8 MHz, MICROCONTROLLER, UUC108 |
| 封裝： | DIE-108 |
| 文件頁數(shù)： | 105/250頁 |
| 文件大小： | 1877K |
| 代理商： | S1C88409D |
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S1C88409 TECHNICAL MANUAL
EPSON
183
CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (A/D Converter)
EAD: A/D conversion completion interrupt
enable register (00FF26HD7)
Enables or disables the A/D conversion comple-
tion interrupt generation to the CPU.
When "1" is written: Interrupt is enabled
When "0" is written: Interrupt is disabled
Reading: Valid
The EAD register is the interrupt enable register
corresponding to the A/D conversion completion
interrupt factor. When this register is set to "1", the
interrupt is enabled, and when it is set to "0", the
interrupt is disabled.
At initial reset, the EAD register is set to "0"
(interrupt is disabled).
FAD: A/D conversion completion interrupt
factor flag (00FF2AHD7)
Indicates the generation of A/D conversion
completion interrupt factor.
When "1" is read: Int. factor has generated
When "0" is read: Int. factor has not generated
When "1" is written: Factor flag is reset
When "0" is written: Invalid
FAD is the interrupt factor flag corresponding to
the A/D conversion completion interrupt. It is set
to "1" when an A/D conversion is completed.
At this point, if the corresponding interrupt enable
register is set to "1" and the corresponding inter-
rupt priority register is set to a higher level than
the setting of the interrupt flags (I0 and I1), an
interrupt is generated to the CPU.
Regardless of the interrupt enable register and
interrupt priority register settings, the interrupt
factor flag is set to "1" when the interrupt genera-
tion condition is met.
To accept the subsequent interrupt after an
interrupt generation, it is necessary to re-set the
interrupt flags (set the interrupt flag to a lower
level than the level indicated by the interrupt
priority registers, or execute the RETE instruction)
and to reset the interrupt factor flag. The interrupt
factor flag is reset to "0" by writing "1".
At initial reset, the FAD flag is reset to "0".
5.18.7 Programming notes
(1) The A/D converter can operate by inputting
the clock from the prescaler. Therefore, it is
necessary to set the division ratio of the
prescaler and to turn the clock output on before
starting A/D conversion. Furthermore, it is
also necessary that the OSC3 oscillation circuit
is operating because the prescaler can operate
only when the OSC3 is set as the CPU clock.
(Refer to Section 5.5, "Prescaler and Clock
Control Circuit for Peripheral Circuits".)
(2) When SLEEP mode is set during A/D conver-
sion, correct A/D conversion result cannot be
obtained because the OSC3 oscillation circuit
stops. Do not set in SLEEP mode during A/D
conversion.
(3) The input clock and analog input terminals
should be set when the A/D converter stops.
Changing in the A/D converter operation may
cause a malfunction.
(4) The frequency of the input clock should be
lower than the maximum value shown in
Section 8.7, "A/D Converter Characteristics".
(5) To prevent malfunction, do not start A/D
conversion (writing to the CHS register) when
the A/D conversion clock is not being output
from the prescaler, and do not turn the
prescaler output clock off during A/D conver-
sion.
(6) If the CHS register selects an input channel
which is not included in the analog input
terminals set by the PAD register (the PAD
register can select several terminals simulta-
neously), the A/D conversion does not result
in a correct converted value.
(7) During A/D conversion, do not operate the
P3n terminals which are not used for analog
inputs of the A/D converter (for input/output
of digital signal and for D/A conversion). It
affects the A/D conversion precision.
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