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參數(shù)資料
| 型號(hào)： | S1C88409D |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 8.8 MHz, MICROCONTROLLER, UUC108 |
| 封裝： | DIE-108 |
| 文件頁(yè)數(shù)： | 114/250頁(yè) |
| 文件大小： | 1877K |
| 代理商： | S1C88409D |
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190
EPSON
S1C88409 TECHNICAL MANUAL
CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and Standby Mode)
5.20.2 Standby mode
The S1C88409 has two standby modes, HALT
mode and SLEEP mode, for saving power. The
following explains each standby mode.
HALT mode
The S1C88409 enters into HALT mode by execut-
ing the HALT instruction.
In HALT mode, the peripheral circuits operate but
the CPU stops operating. Thus, saving power can
be realized.
HALT mode is canceled by initial reset or an
optional interrupt request, and the CPU resumes
program execution from the exception processing
routine.
Refer to the "S1C88 Core CPU Manual" for HALT
status and reactivating sequence.
SLEEP mode
The S1C88409 enters into SLEEP mode by execut-
ing the SLP instruction.
In SLEEP mode, the CPU and the oscillation
circuits (OSC1 and OSC3) stop operating. Conse-
quently, a greater power saving than HALT mode
can be realized.
SLEEP status is canceled by initial reset, NMI or an
input interrupt from the input port. The oscillation
circuit, that has stopped by shifting to SLEEP
mode, resumes oscillating when SLEEP mode is
canceled. The CPU resumes program execution
from the exception processing routine.
5.20.3 Interrupt generation conditions
For all interrupts (10 systems, 22 types) except for
NMI, interrupt factor flags that indicate the
generation of the interrupt factors are provided.
They are set to "1" when the corresponding
interrupt factor is generated.
In addition, interrupt enable registers correspond-
ing to the interrupt factor flags are provided.
Writing "1" to the interrupt enable register enables
the interrupt to the CPU, and writing "0" disables
the interrupt.
The CPU controls interrupt requests with the
interrupt priority level. The priority level of each
interrupt can be set with the interrupt priority
registers, and the CPU accepts only the interrupts
which have a level higher than the setting of the
interrupt flags (I0 and I1).
Therefore, it is necessary to meet the following
three conditions so that the CPU accepts the
interrupt.
(1) The interrupt factor flag has been set to "1" by
generation of an interrupt factor.
(2) The interrupt enable register corresponding to
the interrupt factor has been set to "1".
(3) The interrupt priority register corresponding to
the interrupt factor has been set to a priority
level higher than the interrupt flag (I0 and I1)
setting.
The CPU samples interrupt requests in the first op-
code fetch cycle for every instruction, and shifts to
exception processing when the above mentioned
conditions have been met.
Refer to the "S1C88 Core CPU Manual" for the
exception processing sequence.
Table 5.20.3.1 shows the interrupt factors, interrupt
enable registers and interrupt priority registers
corresponding to the interrupt factors.
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