
208
EPSON
S1C88409 TECHNICAL MANUAL
CHAPTER 8: ELECTRICAL CHARACTERISTICS
8.5 AC Characteristics
8.5.1 External memory access
Read cycle
Item
Address set-up time in read cycle
Address hold time in read cycle
Read signal pulse width
Data input set-up time in read cycle
Data input hold time in read cycle
Address set-up time in read cycle
Address hold time in read cycle
Read signal pulse width
Data input set-up time in read cycle
Data input hold time in read cycle
Address set-up time in read cycle
Address hold time in read cycle
Read signal pulse width
Data input set-up time in read cycle
Data input hold time in read cycle
Address set-up time in read cycle
Address hold time in read cycle
Read signal pulse width
Data input set-up time in read cycle
Data input hold time in read cycle
Note) 1.
Unless otherwise specified:
VDD=5.5 V, VSS=0 V, fOSC1=32.768 kHz, fOSC3=1.0 MHz, Ta=-20 to 70
°C, CL=100 pF,
VIH=0.8VDD, VIL=0.2VDD, VOH=0.8VDD, VOL=0.2VDD
Symbol
tras
trah
trp
trds
trdh
tras
trah
trp
trds
trdh
tras
trah
trp
trds
trdh
tras
trah
trp
trds
trdh
Unit
ns
Note
1
Max.
–
Typ.
–
Min.
tc+tl-200+n*tc/2
th-160
tc-40+n*tc/2
600
0
tc+tl-100+n*tc/2
th-80
tc-20+n*tc/2
300
0
tc+tl-50+n*tc/2
th-40
tc-10+n*tc/2
150
0
tc+tl-50+n*tc/2
th-40
tc-10+n*tc/2
150
0
Substitute the number of states for wait insertion in n.
tc=input clock cycle time, th=input clock H pulse width, tl=input clock L pulse width
Condition
VDD=1.8 to 5.5 V
VD1=1.6 V
VDD=2.6 to 5.5 V
VD1=2.4 V
VDD=3.5 to 5.5 V
VD1=3.2 V
VDD=4.5 to 5.5 V
VD1=4.2 V
ICLK
A00–A21
CE
RD
DIN
VOH
VOL
th *
tras
trah
tc *
VOH
VOL
trp
VIH
VIL
trds
trdh
VIH
tl *
VIL
 In the case of crystal or ceramic oscillation: th=0.5tc±0.05tc, tl=tc-th
In the case of CR oscillation:
th=0.5tc
±0.10tc, tl=tc-th
(1/
tc: oscillation frequency)