
A
B
C
H
E
D
F
G
I
J
K
L
M
N
O
P
Q
R
S
T
U
V W X
Y
Z
PRODUCT SPECIFICATION
Index-17
umul
A-201
umulm
A-202
uneq
A-203
uneqi
A-204
upsampling
horizontal
14-1
vertical
14-1
upscaling
7-12
,
14-1
V
V.34 interface
block diagram
17-2
,
17-3
,
17-4
external pins,table
17-1
programming model
17-8
setup of SSI_CTL register
17-5
test modes
17-8
transmitter logic model
17-5
used as general purpose I/O
17-1
,
17-2
,
17-3
V.34 modem
17-1
vectored interrupts
3-9
vendor ID
PCI interface register
11-3
vertical filter
ICP
14-24
vertical filter parameter table
14-24
vertical filtering
14-1
vertical scaling
14-1
,
14-13
VI_BASE1
alignment
6-10
picture
6-10
VI_BASE2
alignment
6-10
picture
6-10
VI_CAP_SIZE
picture
6-8
VI_CAP_START
picture
6-8
VI_CLK
description table
6-2
VI_CLOCK
picture
6-8
,
6-10
VI_CTL
picture
6-8
,
6-10
VI_DATA
VI_DATA[8]
6-11
VI_DATA[9]
6-11
VI_DATA[7:0]
description table
6-2
VI_DATA[9:8]
description table
6-2
VI_DVALID
description table
6-2
VI_SIZE
picture
6-10
VI_STATUS
picture
6-8
,
6-10
VI_U_BASE_ADR
picture
6-8
VI_UV_DELTA
picture
6-8
VI_V_BASE_ADR
picture
6-8
VI_Y_BASE_ADR
picture
6-8
VI_Y_DELTA
picture
6-8
victim of replacement
5-4
video image data formats
7-9
video in unit
capture parameters
explanation
6-6
picture
6-5
clock generator
6-3
clocking modes
6-3
common source parameters
6-6
connected to 10bit A/D converter
picture
6-3
connected to 8bit CCIR656 camera
picture
6-2
connected to video out
picture
6-3
connected to video recorder
picture
6-3
co-sited sampling
6-4
diagnostic mode
6-2
format of SAV and EAV codes
6-5
fullres capture mode
6-1
description
6-4
halfres capture mode
6-1
description
6-9
halfres co-sited sample capture
picture
6-9
halfres interspersed sample capture
picture
6-9
halfres planar memory format
picture
6-8
highway latency requirements
6-12
highway latency,HBE description
6-12
interface pins
description table
6-2
interspersed sampling
6-5
message passing
major states diagram
6-12
message passing mode