
Philips Semiconductors
DSPCPU Operations for TM1300
PRODUCT SPECIFICATION
A-105
Signed 16-bit load with index
SYNTAX
[ IF rguard ] ild16r rsrc1 rsrc2
→
rdest
FUNCTION
if
rguard
then {
if
PCSW.bytesex = LITTLE_ENDIAN
then
bs
←
1
else
bs
←
0
temp<7:0>
←
mem[(rsrc1+ rsrc2+(1
⊕
bs)]
temp<15:8>
←
mem[(rsrc1+ rsrc2+ (0
⊕
bs)]
rdest
←
sign_ext16to32(temp<15:0>)
}
ATTRIBUTES
Function unit
Operation code
Number of operands
Modifier
Modifier range
Latency
Issue slots
dmem
195
2
No
—
3
4, 5
DESCRIPTION
The
ild16r
operation loads the 16-bit memory value from the address computed by rsrc1+ rsrc2 sign extends it to
32 bits, and stores the result in rdest If the memory address computed by rsrc1+ rsrc2is not a multiple of 2, the result
of
ild16r
is undefined but no exception will be raised. This load operation is performed as little-endian or big-endian
depending on the current setting of the bytesex bit in the PCSW.
The result of an access by
ild16r
to the MMIO address aperture is undefined; access to the MMIO aperture is
defined only for 32-bit loads and stores.
The
ild16r
operation optionally takes a guard, specified in rguard If a guard is present, its LSB controls the
modification of the destination register and the occurrence of side effects. If the LSB of rguardis 1, rdestis written and
the data cache status bits are updated if the addressed locations are cacheable. if the LSB of rguard is 0, rdest is not
changed and
ild16r
has no side effects whatever.
EXAMPLES
Initial Values
Operation
Result
r10 = 0xd00, r20 = 2, [0xd02] = 0x22,
[0xd03] = 0x11
r50 = 0, r40 = 0xd04, r30 = 0xfffffffc,
[0xd00] = 0x84, [0xd01] = 0x33
r60 = 1, r40 = 0xd04, r30 = 0xfffffffc,
[0xd00] = 0x84, [0xd01] = 0x33
r70 = 0xd01, r30 = 0xfffffffc
ild16r r10 r20
→
r80
r80
←
0x00002211
IF r50 ild16r r40 r30
→
r90
no change, since guard is false
IF r60 ild16r r40 r30
→
r100
r100
←
0xffff8433
ild16r r70 r30
→
r110
r110 undefined, since 0xd01 +(–4) is not a
multiple of 2
SEE ALSO
ild16 uld16 ild16d uld16d
uld16r ild16x uld16x
ild16r