
Philips Semiconductors
DSPCPU Operations for TM1300
PRODUCT SPECIFICATION
A-83
Sum of products of signed 16-bit halfwords
SYNTAX
[ IF rguard ] ifir16 rsrc1 rsrc2
→
rdest
FUNCTION
if
rguard
then
rdest
←
sign_ext16to32(rsrc1<31:16>)
×
sign_ext16to32(rsrc2<31:16>) +
sign_ext16to32(rsrc1<15:0>)
×
sign_ext16to32(rsrc2<15:0>)
ATTRIBUTES
Function unit
Operation code
Number of operands
Modifier
Modifier range
Latency
Issue slots
dspmul
93
2
No
—
3
2, 3
DESCRIPTION
As shown below, the
ifir16
operation computes two separate products of the two pairs of corresponding 16-bit
halfwords of rsrc1and rsrc2 the two products are summed, and the result is written to rdest All values are considered
signed; thus, the intermediate products and the final sum of products are signed. All intermediate computations are
performed without loss of precision; the final sum of products is clipped into the range [0x80000000..0x7fffffff] before
being written into rdest
The
ifir16
operation optionally takes a guard, specified in rguard If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguardis 1, rdestis written; otherwise, rdestis not changed.
EXAMPLES
Initial Values
Operation
Result
r30 = 0x00020003, r40 = 0x00010002
r10 = 0, r60 = 0xff9c0064, r70 = 0x0064ff9c
r20 = 1, r60 = 0xff9c0064, r70 = 0x0064ff9c
r30 = 0x00020003, r70 = 0x0064ff9c
ifir16 r30 r40
→
r50
IF r10 ifir16 r60 r70
→
r80
IF r20 ifir16 r60 r70
→
r90
ifir16 r30 r70
→
r100
r50
←
0x8
no change, since guard is false
r90
←
0xffffb1e0
r100
←
0xffffff9c
0
1
3
rsrc1
0
1
3
rsrc2
0
3
rdest
×
×
+
signed
signed
signed
signed
signed
0
3
Clip to [2
31
–1..–2
31
]
Full-precision
33-bit result
signed
SEE ALSO
ifir8ii ifir8ui ufir8uu
ifir16
ifir16