
Philips Semiconductors
DSPCPU Operations for TM1300
PRODUCT SPECIFICATION
A-61
Floating-point subtract
SYNTAX
[ IF rguard ] fsub rsrc1 rsrc2
→
rdest
FUNCTION
if
rguard
then
rdest
←
(float)rsrc1– (float)rsrc2
ATTRIBUTES
Function unit
Operation code
Number of operands
Modifier
Modifier range
Latency
Issue slots
falu
113
2
No
—
3
1, 4
DESCRIPTION
The
fsub
operation computes the difference rsrc1–rsrc2 and writes the result into rdest All values are in IEEE
single-precision floating-point format. Rounding is according to the IEEE rounding mode bits in PCSW. If an argument
is denormalized, zero is substituted for the argument before computing the difference, and the IFZ flag in the PCSW is
set. If the result is denormalized, the result is set to zero instead, and the OFZ flag in the PCSW is set. If
fsub
causes
an IEEE exception, the corresponding exception flags in the PCSW are set. The PCSW exception flags are sticky: the
flags can be set as a side-effect of any floating-point operation but can only be reset by an explicit
writepcsw
operation. The update of the PCSW exception flags occurs at the same time as rdest is written. If any other floating-
point compute operations update the PCSW at the same time, the net result in each exception flag is the logical OR of
all simultaneous updates ORed with the existing PCSW value for that exception flag.
The
fsubflags
operation computes the exception flags that would result from an individual
fsub
.
The
fsub
operation optionally takes a guard, specified in rguard If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest and the exception flags in PCSW are written;
otherwise, rdestis not changed and the operation does not affect the exception flags in PCSW.
EXAMPLES
Initial Values
Operation
Result
r60 = 0xc0400000 (–3.0),
r30 = 0x3f800000 (1.0)
r40 = 0x40400000 (3.0),
r60 = 0xc0400000 (–3.0)
r10 = 0, r40 = 0x40400000 (3.0),
r80 = 0x00800000 (1.17549435e-38)
r20 = 1, r40 = 0x40400000 (3.0),
r80 = 0x00800000 (1.17549435e-38)
r40 = 0x40400000 (3.0),
r81 = 0x00400000 (5.877471754e–39)
r82 = 0x00c00000 (1.763241526e-38),
r83 = 0x0080000 (1.175494351e-38)
r84 = 0x7f800000 (+INF),
r85 = 0x7f800000 (+INF)
r70 = 0x7f7fffff (3.402823466e+38)
r86 = 0xff7fffff (-3.402823466e+38)
r87 = 0xffffffff (QNaN))
r30 = 0x3f800000 (1.0
r87 = 0xffbfffff (SNaN))
r30 = 0x3f800000 (1.0
r83 = 0x0080001 (1.175494421e-38),
r89 = 0x0080000 (1.175494351e-38)
fsub r60 r30
→
r90
r90
←
0xc0800000 (-4.0)
fsub r40 r60
→
r95
r95
←
0x40c00000 (6.0)
IF r10 fsub r40 r80
→
r100
no change, since guard is false
IF r20 fsub r40 r80
→
r110
r110
←
0x40400000 (3.0), INX flag set
fsub r40 r81
→
r111
r111
←
0x40400000 (3.0), IFZ flag set
fsub r82 r83
→
r112
r112
←
0x0, OFZ flag set
fsub r84 r85
→
r113
r113
←
0xffffffff (QNaN), INV flag set
fsub r70 r86
→
r120
r120
←
0x7f800000 (+INF), OVF, INX flag
set
r125
←
0xffffffff (QNaN)
fsub r87 r30
→
r125
fsub r87 r30
→
r125
r125
←
0xffffffff (QNaN), INV flag set
fsub r83 r89
→
r126
r126
←
0x0, UNF flag set
SEE ALSO
fsubflags isub dspisub
dspidualsub readpcsw
writepcsw
fsub