
Philips Semiconductors
DSPCPU Operations for TM1300
PRODUCT SPECIFICATION
A-179
IEEE status flags from convert unsigned integer
to floating-point
SYNTAX
[ IF rguard ] ufloatflags rsrc1
→
rdest
FUNCTION
if
rguard
then
rdest
←
ieee_flags((float) ((unsigned long)rsrc1))
ATTRIBUTES
Function unit
Operation code
Number of operands
Modifier
Modifier range
Latency
Issue slots
falu
128
1
No
—
3
1, 4
DESCRIPTION
The
ufloatflags
operation computes the IEEE exceptions that would result from converting the unsigned integer
in rsrc1 to a single-precision IEEE floating-point value, and an integer bit vector representing the computed exception
flags is written into rdest The bit vector stored in rdest has the same format as the IEEE exception bits in the PCSW.
The exception flags in PCSW are left unchanged by this operation. Rounding is according to the IEEE rounding mode
bits in PCSW.
The
ufloatflags
operation optionally takes a guard, specified in rguard If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguardis 1, rdestis written; otherwise, rdestis not changed.
EXAMPLES
Initial Values
Operation
Result
r30 = 3
r40 = 0xffffffff (4294967295)
r10 = 0, r50 = 0xfffffffd
r20 = 1, r50 = 0xfffffffd
r60 = 0x7fffffff (2147483647)
r70 = 0x80000000 (2147483648)
r80 = 0x7ffffff1 (2147483633)
ufloatflags r30
→
r100
ufloatflags r40
→
r105
IF r10 ufloatflags r50
→
r110
IF r20 ufloatflags r50
→
r115
ufloatflags r60
→
r117
ufloatflags r70
→
r120
ufloatflags r80
→
r122
r100
←
0
r105
←
0x02 (INX)
no change, since guard is false
r115
←
0x02 (INX)
r117
←
0x02 (INX)
r120
←
0
r122
←
0x02 (INX)
OFZ
IFZ
INV
OVF
UNF
INX
DBZ
0
1
2
3
4
5
6
7
0
31
0
SEE ALSO
ufloat ifloatflags
ifloatrzflags
ufloatrzflags
ufloatflags