
Philips Semiconductors
DSPCPU Operations for TM1300
PRODUCT SPECIFICATION
A-45
Floating-point compare greater or equal
SYNTAX
[ IF rguard ] fgeq rsrc1 rsrc2
→
rdest
FUNCTION
if
rguard
then {
if
(float)rsrc1>= (float)rsrc2
then
rdest
←
1
else
rdest
←
0
}
ATTRIBUTES
Function unit
Operation code
Number of operands
Modifier
Modifier range
Latency
Issue slots
fcomp
146
2
No
—
1
3
DESCRIPTION
The
fgeq
operation sets the destination register, rdest to 1 if the first argument, rsrc1 is greater than or equal to
the second argument, rsrc2 otherwise, rdest is set to 0. The arguments are treated as IEEE single-precision floating-
point values; the result is an integer. If an argument is denormalized, zero is substituted for the argument before
computing the comparison, and the IFZ flag in the PCSW is set. If
fgeq
causes an IEEE exception, the
corresponding exception flags in the PCSW are set. The PCSW exception flags are sticky: the flags can be set as a
side-effect of any floating-point operation but can only be reset by an explicit
writepcsw
operation. The update of the
PCSW exception flags occurs at the same time as rdest is written. If any other floating-point compute operations
update the PCSW at the same time, the net result in each exception flag is the logical OR of all simultaneous updates
ORed with the existing PCSW value for that exception flag.
The
fgeqflags
operation computes the exception flags that would result from an individual
fgeq
.
The
fgeq
operation optionally takes a guard, specified in rguard If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest and the exception flags in PCSW are written;
otherwise, rdestis not changed and the operation does not affect the exception flags in PCSW.
EXAMPLES
Initial Values
Operation
Result
r30 = 0x40400000 (3.0), r40 = 0 (0.0)
r30 = 0x40400000 (3.0)
r10 = 0, r60 = 0x3f800000 (1.0),
r30 = 0x40400000 (3.0)
r20 = 1, r60 = 0x3f800000 (1.0),
r30 = 0x40400000 (3.0)
r30 = 0x40400000 (3.0),
r60 = 0x3f800000 (1.0)
r30 = 0x40400000 (3.0),
r61 = 0xffffffff (QNaN)
r50 = 0x7f800000 (+INF)
r55 = 0xff800000 (-INF)
r60 = 0x3f800000 (1.0),
r65 = 0x00400000 (5.877471754e-39)
r50 = 0x7f800000 (+INF)
fgeq r30 r40
→
r80
fgeq r30 r30
→
r90
IF r10 fgeq r60 r30
→
r100
r80
←
1
r90
←
1
no change, since guard is false
IF r20 fgeq r60 r30
→
r110
r110
←
0
fgeq r30 r60
→
r120
r120
←
1
fgeq r30 r61
→
r121
r121
←
0, INV flag set
fgeq r50 r55
→
r125
r125
←
1
fgeq r60 r65
→
r126
r126
←
1, IFZ flag set
fgeq r50 r50
→
r127
r127
←
1
SEE ALSO
igeq fgeqflags fgtr
readpcsw writepcsw
fgeq