
A
B
C
H
E
D
F
G
I
J
K
L
M
N
O
P
Q
R
S
T
U
V W X
Y
Z
Index-8
PRODUCT SPECIFICATION
ifixieeeflags
A-87
ifixrz
A-88
ifixrzflags
A-89
iflip
A-90
ifloat
A-91
ifloatflags
A-92
ifloatrz
A-93
ifloatrzflags
A-94
igeq
A-95
igeqi
A-96
igtr
A-97
igtri
A-98
iimm
A-99
iis
8-1
ijmpf
A-100
ijmpi
A-101
ijmpt
A-102
ild16
A-103
ild16d
A-104
ild16r
A-105
ild16x
A-106
ild8
A-107
ild8d
A-108
ild8r
A-109
ileq
A-110
ileqi
A-111
iles
A-112
ilesi
A-113
image
ICP input format
14-3
processing algorithms
14-6
resizing
14-6
scaling
14-6
scaling factor range
14-3
size range
14-3
Image co-processor
block diagram
14-1
image co-processor
14-1
block diagram
14-2
image formats
14-3
image overlay
14-1
,
14-5
,
14-9
image overlay formats
of ICP,table
14-5
image processing
bandwidth
14-1
IMASK
picture
3-11
imax
A-114
imin
A-115
imul
A-116
imulm
A-117
ineg
A-118
ineq
A-119
ineqi
A-120
initialization
DRAM memory system
12-5
instruction cache
5-10
initialization,cache
5-8
inonzero
A-121
input format
ICP
14-3
input grid
relating to output grid
14-7
instruction breakpoint
3-13
instruction cache
5-8
address mapping
5-8
picture
5-9
coherency
5-11
initialization and boot
5-10
LRU replacement
5-11
performance evaluation support
5-12
instruction cache parameters
5-8
instruction cache set
5-8
instruction cache tag
5-8
instruction cache,summary
5-8
INT_CTL
PCI interface MMIO register
11-15
picture
3-12
,
11-10
integer representation
3-4
interleaving
of SDRAM
12-5
interrupt line
PCI interface register
11-9
interrupt mask
3-10
interrupt mode
3-10
interrupt pin
PCI interface register
11-9
interrupt priority
3-10
interrupt vectors
3-9
interrupts
3-9
definition
3-9
DSPCPU enable bit
3-2
interspersed sampling
6-5
intervals
refresh
12-6
INTVEC[31:0]
picture
3-9
IO_ADR
PCI interface MMIO register
11-13
picture
11-10
IO_CTL
PCI interface MMIO register
11-13
picture
11-10
IO_DATA
PCI interface MMIO register
11-13
picture
11-10