
TM1300 Data Book
Philips Semiconductors
12-4
PRODUCT SPECIFICATION
external input clock TRI_CLKIN; the PLL output deter-
mines the operating frequency of the memory interface
and SDRAM devices. The default value is ‘0’, which im-
plies a 2:1 memory:external ratio. A value of ‘1’ implies a
3:1 ratio.
CD (CPU PLL disable).
The 1-bit CD field determines
whether or not the CPU PLL is turned on. The reset value
is ‘1’, which disables operation of the CPU PLL and dis-
sipates almost no power. For normal operation the value
should be zero, enabling the CPU PLL.
CB (CPU PLL bypass).
The 1-bit CB field determines
whether the input or the output of the CPU PLL drives
TM1300’s core logic. The default value is ‘1’, which caus-
es the TM1300 core to be clocked by the input of the
CPU PLL (i.e., the memory interface clock). A value of ‘0’
causes normal operation, and the core is clocked by the
output of the CPU PLL.
Note that if both CB and SB are set to ‘1’ (bypass the
CPU PLL and the SDRAM PLL), TM1300’s core logic is
effectively clocked at the external input frequency.
Note: it is illegal to use the output of a disabled PLL. For
example, it is illegal to have CD set to ‘1’ while CB is set
to ‘0’.
SD (SDRAM PLL disable).
The 1-bit SD field deter-
mines whether or not the SDRAM PLL is turned on. The
default value is ‘1’, which disables the SDRAM PLL. In
this state, it dissipates almost no power. For normal op-
eration the value should be ‘0’, enabling the SDRAM
PLL.
SB (SDRAM PLL bypass).
The 1-bit SB field deter-
mines whether the input or the output of the SDRAM PLL
drives the memory interface and memory devices. The
default value is ‘1’, which causes the memory system to
be clocked by the input of the SDRAM PLL (TM1300’s
external input clock). A value of ’0’ causes normal oper-
ation, and the memory system is clocked by the output of
the SDRAM PLL.
Table 12-3. Examples of Memory Configurations
Size
(MB)
Ranks
Rank Configurations
Max.
MHz
Peak
MB/s
8
1
2
four 2
×
1M
×
8 SDRAM
two 2
×
512K
×
16 SDRAM
two 2
×
512K
×
16 SDRAM
one 4
×
512K
×
32 SDRAM
two 4
×
1M
×
16 SDRAM
one 4
×
512K
×
32 SDRAM
one 4
×
512K
×
32 SDRAM
one 4
×
512K
×
32 SDRAM
one 4
×
512K
×
32 SDRAM
one 4
×
512K
×
32 SDRAM
two 4
×
2M
×
16 SDRAM
four 4
×
2M
×
8 SDRAM
two 4
×
1M
×
16 SDRAM
two 4
×
1M
×
16 SDRAM
one 4
×
512K
×
32 SDRAM
one 4
×
512K
×
32 SDRAM
one 4
×
512K
×
32 SDRAM
one 4
×
512K
×
32 SDRAM
two 4
×
1M
×
16 SDRAM
two 4
×
1M
×
16 SDRAM
two 4
×
1M
×
16 SDRAM
two 4
×
1M
×
16 SDRAM
two 4
×
1M
×
16 SDRAM
two 4
×
1M
×
16 SDRAM
two 4
×
1M
×
16 SDRAM
143
143
572
572
1
1
2
143
143
143
572
572
572
16
24
3
143
572
32
1
1
2
143
143
143
572
572
572
4
143
572
48
3
133
532
64
4
133
500
Table 12-4. Memory Interface Configuration
Registers
Register
Purpose
MM_CONFIG
PLL_RATIOS
Describes external memory configuration
Controls separate memory and CPU PLLs
(phase-locked loops)
Table 12-5. MM_CONFIG Fields
Field
Function
REFRESH
Refresh interval in memory clock cycles.
Default value 1000 (0x03E8).
Memory rank size
SIZE
0
1
2
3
4
5
6
7
Reserved
512KB
1MB
2MB
4MB
8MB
16MB
Reserved
Table 12-6. PLL_RATIOS Fields
Field
Function
CR
CPU:memory ratio
0
1
2
3
4
1:1
2:1
3:2
4:3
5:4
5–7 Reserved
0
2:1
1
3:1
0
CPU PLL on
1
CPU PLL off
0
CPU
←
PLL
1
CPU
←
Memory
0
SDRAM PLL on
1
SDRAM PLL off
0
Memory
←
PLL
1
Memory
←
external
SR
Memory:external ratio
CD
CPU PLL Disable
CB
CPU PLL bypass
SD
SDRAM PLL Disable
SB
SDRAM PLL bypass