
A
B
C
H
E
D
F
G
I
J
K
L
M
N
O
P
Q
R
S
T
U
V W X
Y
Z
PRODUCT SPECIFICATION
Index-5
dspidualsub
A-27
dspimul
A-28
dspisub
A-29
dspuadd
A-30
dspumul
A-31
dspuquadaddui
A-32
dspusub
A-33
dual port
5-4
E
EAV and SAV codes
description
7-5
EAV format
6-5
edge sensitive interrupts
3-10
endian-ness
5-4
endianness
3-2
Enhanced Video Out
7-1
Enhanced Video Out Unit
active video definition
picture
7-6
algorithms,overview
7-11
alpha blending
7-13
block diagram
7-3
CCIR 656 frame timing
description
7-6
description table
7-6
CCIR 656 line timing
description
7-4
picture
7-5
CCIR 656 pixel timing
description
7-4
picture
7-5
clock system
7-24
picture
7-3
connection to video encoder,picture
7-2
connection to video in unit,picture
7-3
connection,CCIR656,picture
7-2
data streaming
7-22
data transfer timing
7-8
dds
7-24
DDS and PLL setting,examples
7-25
error conditions
7-23
field definition
picture
7-6
frame definition
picture
7-6
frame timing signals
7-7
functions,summary
7-1
graphics overlay
7-22
graphics overlay formats
7-10
horizontal timing signals
7-7
image addressing
7-22
image definition
picture
7-6
image timing
7-4
interrupts
7-23
message passing
7-22
MMIO registers
7-14
NTSC
7-16
operating modes
7-13
operation,description
7-20
overlay definition
picture
7-6
PAL
7-16
pixel mirroring
7-12
PLL filter
block diagram
7-24
pll filter
7-24
progressive scan
7-6
summary of functions
7-1
timing generation
description
7-6
timing register
recommended values
7-21
video image data formats
7-9
YUV image format
7-9
YUV planar format
7-9
YUV upscaling
7-12
Enhanced Video Out unit
block diagram
7-3
clock system
7-3
interface pins
7-2
EVO
Enhanced Video Out Unit
7-1
EVO_CLIP
field description table
7-21
picture
7-20
EVO_CTL
field description table
7-21
picture
7-20
EVO_KEY
field description table
7-21
picture
7-20
EVO_MASK
field description table
7-21
picture
7-20
EVO_SLVDLY
field description table
7-21
picture
7-20
exceptions
definition
3-9
expansion ROM base address
PCI interface register
11-9