參數(shù)資料
型號: PCA5010H
廠商: NXP Semiconductors N.V.
英文描述: Pager baseband controller
中文描述: 傳呼機(jī)基帶控制器
文件頁數(shù): 98/112頁
文件大小: 627K
代理商: PCA5010H
1998 Nov 02
98
Philips Semiconductors
Product specification
Pager baseband controller
PCA5010
15.2.1
S
IGNALS FOR THE PARALLEL PROGRAMMING MODE
In this configuration, the following signals are necessary to program the OTP:
Table 63
Pins for programming mode
The control signals GBMbpB, PGM, LS1 and LS0 can be used to select the latches of the interface block and the internal
data latches of the OTP. Table 64 shows how the latches are selected.
RdStrb is used to open the selected latch. If PGM is not active the RdSTrb signal is used to start the OTP read cycle.
Table 64
Latch selection
OTP PIN
TYPE
EPROM PIN
DESCRIPTION
COMMENTS
V
PP
supply
V
PP
programming
voltage
positive supply
negative supply
address
data-output
data-input
security bits input
security bits output
latch select 0
latch select 1
programming mode
read/strobe
special pin/logic signal not time critical
V
DD
GND
P0.7 to P0.0
supply
supply
IO
V
DD
GND
A<14:0>
Q<7:0>
I<7:0>
PS<2:0>
QS<2:0>
CEP/MBPC
32 kbytes addresses available
connected to P0.2 to P0.0 pins
P2.0/LS0
P2.1/LS1
P2.2/PGM
P2.3/RdStrb
input
input
input
input
latch select signals, see Table 64
read enable clock (CEP) when PGM = 0;
strobe for the latches when PGM = 1
read EPROM and set P0 as output; multiple
byte programming when PGM = 1
programs data if V
PP
is present
see Section 15.10
P2.4/GBMbpB input
GB
output enable not/
Mult.BProg Not
write enable not
select security bits
read signature bytes see Section 15.9
P2.5/WEB
P2.6/SEC
P2.7/SIG
input
input
input
WEB
SEC
SIG
P2.4/GBMbpB
P2.2/PGM
P2.1/LS1
P2.1/LS0
DESCRIPTION
X
1
X
X
0
0
1
1
1
1
X
0
0
1
1
X
0
1
0
1
no latches selected
select test control latch
select lower address latch
select upper address latch
select internal data latch in multi byte programming
mode
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