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| 型號(hào)： | PCA5010H |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Pager baseband controller |
| 中文描述： | 傳呼機(jī)基帶控制器 |
| 文件頁數(shù)： | 95/112頁 |
| 文件大?。?/td> | 627K |
| 代理商： | PCA5010H |
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1998 Nov 02
95
Philips Semiconductors
Product specification
Pager baseband controller
PCA5010
14 APPENDIX 1: SPECIAL MODES OF THE PCA5010
14.1
Overview
During the rising edge of the external RESOUT signal, the
state of the pins ALE, PSEN, EA and P2.X is sampled and
stored. The following decoding (ALE, PSEN and P2) is
used to force the PCA5010 into different operating modes:
[1, 1, X]
→
RUN mode
[0, 1, X]
→
EMUlation modes (for P2 decoding refer to
Metalink documents)
[1, 0, Y]
→
test mode, submode Y
[0, 0, X]
→
OTP parallel programming mode.
The customer will usually only see the normal RUN mode.
14.2
OTP parallel programming mode
The OTP parallel programming mode is used to access the
on-chip OTP directly from the device pins for programming
and verification. The OTP parallel programming mode and
its initialization are explained in detail in Chapter 15.
14.3
Test modes
The test modes of the PCA5010 are used during the
production test of the circuit. Test modes are not intended
to be used by customers except test mode 2, the
demodulator and clock recovery test mode.
Test mode 2 may be used by customers for BER
measurements in closed-loop systems. The following
application diagram (see Fig.66) shows an application
which enters this mode during start-up. After the test mode
is entered the PCA5010 starts execution of code from the
internal program memory. This code must enable the
demodulator and clock recovery in the required modes.
If the microcontroller is requested to make port I/O, then a
frequency of approximately 6 MHz with V
DD
level needs to
be supplied at the TCLK pin.
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