參數(shù)資料
型號: PCA5010H
廠商: NXP Semiconductors N.V.
英文描述: Pager baseband controller
中文描述: 傳呼機基帶控制器
文件頁數(shù): 58/112頁
文件大小: 627K
代理商: PCA5010H
1998 Nov 02
58
Philips Semiconductors
Product specification
Pager baseband controller
PCA5010
6.19.8
I
NTERRUPT HANDLING
Figure 34 shows the conventions for interrupt assignments and priorities.
Arbitration of several simultaneously sampled interrupts can be seen from Fig.34. The sampled interrupt with the highest
priority will be handled first (assuming that the Interrupt Priority is default).
Setting of interrupt request flags for X2 to X9 is masked by the corresponding interrupt enable bit (IEN1).
Fig.34 Interrupt assignment and priorities.
Note: The signal level applied to the EA pin defines whether the interrupt vector code is fetched from external or internal ROM.
handbook, full pagewidth
MGR130
high
IP0/1
IEN0/1
low
0.0
0.0
TCON.1
IE0
0.5
0.5
S1CON.3
SI
1.3
1.3
IRQ1.3
SYM
0.1
0.1
TCON.5
TF0
0.6
0.6
WUCON.6
WUP
1.4
1.4
IRQ1.4
IQ6
0.2
0.2
TCON.3
IE1
1.0
1.0
IRQ.0
IQ2
1.5
1.5
IRQ1.5
DC
0.3
0.3
TCON.7
TF1
1.1
1.1
IRQ1.1
IQ3
1.6
1.6
IRQ1.6
WDI
0.4
0.4
S0CON.0/1
TI/RI
1.2
1.2
IRQ1.2
IQ4
1.7
1.7
RTCON.7
MIN
0.7
X0
S1
X5
T0
T2
X6
X1
X2
X7
T1
X3
X8
S0
X4
X9
P3.2
P1.4
P3.3
P1.0
P1.1
P1.2
INT0
I
2
C-bus
SymClk
Timer 0
Wake-up
INT6
INT1
INT2
DC/DC
Timer 1
INT3
WDINT
UART
INT4
MINUTE
HW
SW
SW
HW
SW
SW
HW
SW
SW
HW
SW
SW
SW
SW
SW
03
Name
Flag
Port
function
by
2B
53
0B
33
5B
13
3B
63
1B
43
6B
23
4B
73
global
enable
decreasing
priority
within
same
level
PRIORITY
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