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參數(shù)資料
| 型號(hào)： | PCA5010H |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Pager baseband controller |
| 中文描述： | 傳呼機(jī)基帶控制器 |
| 文件頁數(shù)： | 37/112頁 |
| 文件大小： | 627K |
| 代理商： | PCA5010H |
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1998 Nov 02
37
Philips Semiconductors
Product specification
Pager baseband controller
PCA5010
Table 27
RTC Control Register (RTCCON, SFR address CDH)
Table 28
Description of the RTCON bits
6.13.3
R
EAL
-T
IME
C
LOCK
D
ATA
R
EGISTER
(RTC0)
Table 29
RTC Data Register (RTC0, SFR address CEH)
The value stored in this SFR is the actual 4 Hz count since the last MINUTE interrupt. The contents of this counter can
be read from and written to by software. The contents of this counter are only initialized when RESETIN is activated.
During an OFF sequence, the RTC continues its operation.
The value of the RTC data register is only updated while the STB flag in the DCCON0 SFR is HIGH, i.e. the DC/DC
converter is able to sustain the V
DD
supply voltage. If the STB flag is logic 0 the real-time clock continues its operation,
the MINUTE interrupt occurs regularly, but the SFR is not updated.
7
6
5
4
3
2
1
0
MIN
W/R
LOAD
SET
BIT
SYMBOL
FUNCTION
RTCON.7
MIN
MIN is activated when the counter reaches 239
. MIN is used to generate the interrupt
request signal MINUTE. In order to complete the interrupt cycle and reset the interrupt
source, the processor has to clear MIN. This must be done in a 2 step operation writing
MIN and then applying a positive edge to SET.
unused
unused
unused
unused
Before the RTC time can be set by software, the updating of the SFR by the RTC must
be disabled. This is done by writing the W/R bit to logic 1. The W/R bit is cleared by
hardware after the next 4 Hz clock, when the RTC has been loaded with its next value.
Load RTC with contents of RTC0
. LOAD is sampled with the positive edge of the set
flag SET. If LOAD is not HIGH during a SET operation, only the MIN flag is (re)set by the
command.
Latch signal for the real-time clock
. With the pulse on SET the content of MIN is
copied into the ‘real’ MIN latch. This is necessary because the RTC has to be active at
all times independant of the microcontroller.
RTCON.6
RTCON.5
RTCON.4
RTCON.3
RTCON.2
W/R
RTCON.1
LOAD
RTCON.0
SET
7
6
5
4
3
2
1
0
QSECS7
QSECS6
QSECS5
QSECS4
QSECS3
QSECS2
QSECS1
QSECS0
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