參數(shù)資料
型號(hào)： PCA5010H
廠商： NXP Semiconductors N.V.
英文描述： Pager baseband controller
中文描述： 傳呼機(jī)基帶控制器
文件頁數(shù)： 60/112頁
文件大?。?/td> 627K
代理商： PCA5010H
1998 Nov 02
60
Philips Semiconductors
Product specification
Pager baseband controller
PCA5010
Each of these events first starts the DC/DC converter to
ramp up V
DD
to 2.2 V. After an initial reset, generated by
the DC/DC converter when V
DD
is again at normal level, all
2 V blocks will restart their operation. The first instruction
will be fetched from address 0.
The edge sensitive interrupts (minute and wake-up) from
the internal sources have been lost during restart and must
be polled from their SFRs. Events from P1 pins can be
served after enabling the interrupts, since they are level
sensitive.
6.20.4
S
TATUS OF EXTERNAL PINS
The status of the external pins during Idle and power-down
mode is shown in Table 51.
Table 51
Status of external pins during normal, Idle and power-down modes
6.20.5
P
OWER
C
ONTROL
R
EGISTER
(PCON)
The reduced power modes are activated by software using this special function register. PCON is not bit addressable.
Table 52
Table 53
Power Control Register (PCON, SFR address 87H)
Notes
1.
This device does not support external XRAM access. Therefore the XRE bit is meaningless and should never be
written to logic 1.
MODE
MEMORY
ALE
PSEN
PORT 0
PORT 1
PORT 2
PORT 3
Normal
Idle
internal
internal
external
internal
external
0
1
1
0
0
1
1
1
0
0
port data
port data
pull-up HIGH
pull-up HIGH
pull-up HIGH
port data
port data
port data
port data
port data
port data
port data
address
port data
address
port data
port data
port data
port data
port data
Power-down
7
6
5
4
3
2
1
0
SMOD
XRE
ENIS
GF1
GF0
PD
IDL
BIT
SYMBOL
SMOD
XRE
FUNCTION
PCON.7
PCON.6
Control bit to double data rate of UART, when set to logic 1.
If set to logic 1 enables external XRAM from address 0 on, if set to logic 0 the first
1024 XRAM bytes are in internal XRAM, the higher addresses come from external
XRAM; see note 1.
Enable ISYNC
. If bit is set, ISYNC can be monitored at pin EA in internal access mode.
The binary value of ISYNC changes each time a new instruction is fetched from
memory. This bit must not be set to logic 1 by user program!
Reserved.
General purpose flag bit
.
General purpose flag bit
.
Power-down bit
. Setting this bit activates the power-down mode; see note 2.
Idle mode bit
. Setting this bit activates the Idle mode; see note 2.
PCON.5
ENIS
PCON.4
PCON.3
PCON.2
PCON.1
PCON.0
GF1
GF0
PD
IDL
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