參數(shù)資料
型號: PCA5010H
廠商: NXP Semiconductors N.V.
英文描述: Pager baseband controller
中文描述: 傳呼機基帶控制器
文件頁數(shù): 48/112頁
文件大?。?/td> 627K
代理商: PCA5010H
1998 Nov 02
48
Philips Semiconductors
Product specification
Pager baseband controller
PCA5010
6.17.2
D
EMODULATOR
C
ONTROL
R
EGISTER
(DMD0)
The demodulator control register DMD0 contains the control bits for enabling the demodulator function and setting its
mode and data rate.
Table 38
Demodulator Control Register (DMD0, SFR address ECH)
Table 39
Description of the DMD0 bits
Table 40
Baud rate for bits BD2, BD1 and BD0
6.17.3
D
EMODULATOR AVERAGING
R
EGISTER
(DMD1)
The demodulator averaging register DMD1 contains the control bit for enabling the averaging function, used for the offset
compensation during demodulation and the coded average (offset) value.
Table 41
Demodulator averaging Register (DMD1, SFR address EDH)
7
6
5
4
3
2
1
0
ENB
M
RES
LEV
BD2
BD1
BD0
BIT
SYMBOL
FUNCTION
DMD0.7
DMD0.6
DMD0.5
DMD0.4
DMD0.3
DMD0.2
DMD0.1
DMD0.0
ENB
M
RES
LEV
BD2
BD1
BD0
enable demodulator function
mode selection: logic 0 = I/Q from zero-IF receiver, logic 1 = NRZ data
not used
reserved for future implementation
if set to logic 0 2-FSK demodulation, if set to logic 1 4-FSK demodulation
baud rate setting; see Table 40
BITS
BAUD RATE
BD2
BD1
BD0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1200 symbols/s
2400 symbols/s
1600 symbols/s
3200 symbols/s
undefined
undefined
undefined
3125 symbols/s
7
6
5
4
3
2
1
0
ENA
AVG6
AVG5
AVG4
AVG3
AVG2
AVG1
AVG0
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