參數(shù)資料
型號(hào)： PCA5010H
廠商： NXP Semiconductors N.V.
英文描述： Pager baseband controller
中文描述： 傳呼機(jī)基帶控制器
文件頁數(shù)： 52/112頁
文件大?。?/td> 627K
代理商： PCA5010H
1998 Nov 02
52
Philips Semiconductors
Product specification
Pager baseband controller
PCA5010
6.19.2
I
NTERRUPT PROCESS
Sample the interrupt lines:
The interrupt lines are
latched at the beginning of each instruction cycle.
Analyse the requests:
The sampled interrupt lines will be
analysed with respect to the relevant Interrupt Enable
register (IEx) and Interrupt Priority register (IPx).
The process will deliver the vector of the highest interrupt
request and the priority information. Depending on the
interrupt level and the priority of the interrupt in progress,
an interrupt request to the core is performed. The vector
address will be passed to the core process.
Interrupt request to core:
Level 0:
The interrupt request to the core is performed,
when at least one instruction is performed since the
RETI from Level 1.
Level 1:
The interrupt request is performed, when at
least one instruction is performed since the RETI from
Level 21 and the request has high priority.
Level 20:
No request is performed.
Level 21:
No request is performed.
Emulation:
In break mode no interrupt request is
performed.
Update the interrupt level:
Level 0:
In the event of a high priority interrupt the new
level will be Level 20. If it is a low priority interrupt, the
new level will be Level 1.
Level 1:
In the event of a high priority interrupt, the new
level will be Level 21. A low priority interrupt is not
performed, the level is unchanged. On RETI the new
level will be Level 0.
Level 20:
On RETI, the new level is Level 0.
Level 21:
On RETI, the new level is Level 1.
Level 1:
On RETI, the new level is Level 0.
Level 0:
The new level is Level 0.
Clearing the flags:
During the forced LCALL the interrupt
flag of the relevant interrupt is cleared by hardware, if
applicable, otherwise by software.
Emulation:
During emulation the interrupts may be
disabled. This is performed during break mode. With INTD
asserted, all the interrupts are disabled.
Idle and power-down:
When Idle (PCON.0) or
power-down (PCON.1) is set, the interrupt controller waits
for the according WUI signal. Because the interrupt
controller is waiting for WUI, all activity in the circuit will be
stopped, thus no handshake can be completed. The WUI
signal for Idle is the OR of all the interrupt request bits and
the reset. For power-down the WUI signal is built only with
the Port 1 interrupt request flags and the reset.
6.19.3
I
NTERRUPT CONTROLLER RELATED
SFR
S
The implementation of the interrupt controller related
SFRs for enabling and disabling interrupts is identical to a
standard 80C51, but the interrupt sources have been
changed according to Table 50.
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