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參數(shù)資料
| 型號(hào)： | PCA5010H |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Pager baseband controller |
| 中文描述： | 傳呼機(jī)基帶控制器 |
| 文件頁數(shù)： | 23/112頁 |
| 文件大?。?/td> | 627K |
| 代理商： | PCA5010H |
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1998 Nov 02
23
Philips Semiconductors
Product specification
Pager baseband controller
PCA5010
Table 8
Description of the S1CON bits
6.8.4
D
ATA
S
HIFT
R
EGISTER
(S1DAT)
S1DAT contains the serial data to be transmitted or data which has just been received. Bit 7 is transmitted or received
first; i.e. data shifted from left to right.
Table 9
Data Shift Register (S1DAT, SFR address DAH)
6.8.5
A
DDRESS
R
EGISTER
(S1ADR)
The slave address register is not available since slave mode is not supported.
BIT
SYMBOL
ENS1
FUNCTION
S1CON.7
S1CON.6
CR2 is not available.
Enable serial I/O
. When ENS1 = 0, the serial I/O is disabled. SDA and SCL outputs are
in the high-impedance state; P1.6 and P1.7 function as open-drain ports. When
ENS1 = 1, the serial I/O is enabled. Output port latches P1.6 and P1.7 must be set to
logic 1.
START flag
. If STA is set while the SIO is in master mode, SIO will generate a repeated
START condition.
STOP flag
. With this bit set while in master mode a STOP condition is generated. When
a STOP condition is detected on the I
2
C-bus, the SIO hardware clears the STO flag.
SIO interrupt flag
. This flag is set, and an interrupt is generated, after any of the
following events occur:
A START condition is generated in master mode
A data byte has been received or transmitted in master mode (even if arbitration is
lost).
If this flag is set, the I
2
C-bus is halted (by pulling down SCL). Received data is only valid
until this flag is reset.
Assert Acknowledge
. When this bit is set, an acknowledge (LOW level to SDA) is
returned during the acknowledge clock pulse on the SCL line when:
A data byte is received while the device is programmed to be a master receiver.
When this bit is reset, no acknowledge is returned.
CR1 is not available.
Speed selection (with on-chip 6 MHz oscillator tuned to 6 MHz the nominal bus
frequency is:
CR0 = 0 is 83.3 kHz (6 MHz divided-by-72)
CR0 = 1 is 333 kHz (6 MHz divided-by-18).
S1CON.5
STA
S1CON.4
STO
S1CON.3
SI
S1CON.2
AA
S1CON.1
S1CON.0
CR0
7
6
5
4
3
2
1
0
D7
D6
D5
D4
D3
D2
D1
D0
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