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參數(shù)資料
| 型號(hào)： | MT90500 |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | Multi-Channel ATM AAL1 SAR(多通道 ATM AAL1分段及重組設(shè)備（基于通訊總線的系統(tǒng)與ATM網(wǎng)絡(luò)的接口）) |
| 中文描述： | 多通道自動(dòng)柜員機(jī)AAL1特區(qū)（多通道自動(dòng)柜員機(jī)AAL1分段及重組設(shè)備（基于通訊總線的系統(tǒng)與空中交通管理網(wǎng)絡(luò)的接口）） |
| 文件頁(yè)數(shù)： | 87/159頁(yè) |
| 文件大小： | 514K |
| 代理商： | MT90500 |
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MT90500
87
5.2.2
TX_SAR Registers
Table 17 - TX_SAR Control Register
Address: 2000 (Hex)
Label: TXSC
Reset Value: 0000 (Hex)
Label
Bit Position
Type
Description
SAENA
0
R/W
Scheduler A Enable. ‘0’ = Disabled; ‘1’ = Enabled. Before enabling this scheduler, all its
configuration registers must be written and valid. These registers must not be changed
while SAENA is HIGH. If an event scheduler is re-configured (i.e. changes made to 2010h,
2012h, or 2014h), all of its events and dependent structures should be re-initialized before
starting the scheduler again.
SBENA
1
R/W
Scheduler B Enable. ‘0’ = Disabled; ‘1’ = Enabled. Before enabling this scheduler, all its
configuration registers must be written and valid. These registers must not be changed
while SBENA is HIGH. If an event scheduler is re-configured (i.e. changes made to 2020h,
2022h, or 2024h), all of its events and dependent structures should be re-initialized before
starting the scheduler again.
SCENA
2
R/W
Scheduler C Enable. ‘0’ = Disabled; ‘1’ = Enabled. Before enabling this scheduler, all its
configuration registers must be written and valid. These registers must not be changed
while SCENA is HIGH. If an event scheduler is re-configured (i.e. changes made to 2030h,
2032h, or 2034h), all of its events and dependent structures should be re-initialized before
starting the scheduler again.
TXFFENA
3
R/W
Transmit FIFO Enable. When this bit is LOW, the Transmit Data Cell FIFO Read Pointer
(TXFFRP in TXDFRP at 2054h) is reset to 00h. When this bit is HIGH, the FIFO can
operate normally.
AUTODATA
4
R/W
When this bit is ‘1’, non-CBR data cells (the next cells located in the Transmit Data Cell
FIFO) will be transmitted while the TX_SAR is idle. When this bit is ‘0’, data cell
transmission is controlled by the schedulers.
TXFFORIE
5
R/W
Transmit Data Cell FIFO Overrun Error Interrupt Enable. ‘0’ = Disabled; ‘1’ = Enabled.
When enabled, a ‘1’ on TXFFOR in Register 2002h will force a ‘1’ on TX_SAR_SERV in
Register 0002h.
SCHEDULE_IE
6
R/W
Scheduler Error Interrupt Enable. ‘0’ = Disabled; ‘1’ = Enabled. When enabled, a ‘1’ on
SCHEDULE in Register 2002h will force a ‘1’ on TX_SAR_SERV in Register 0002h.
TXFFRP+
7
R/W
Increment Transmit Data Cell FIFO Read Pointer. When ‘1’ is written to this bit, the
Transmit Data Cell FIFO Read Pointer (TXFFRP) is incremented. Used for test purposes
only.
TESTS
8
R/W
Test Status. When HIGH, this bit forces all the status events in TX_SAR Status Register at
2002h to occur. Used for test purposes only.
Reserved
15:9
R/O
Reserved. Always read as “0000_000”.
Table 18 - TX_SAR Status Register
Address: 2002 (Hex)
Label: TXSS
Reset Value: 0000 (Hex)
Label
Bit
Position
Type
Description
Reserved
4:0
R/O
Reserved. Always read as “0_0000”.
TXFFOR
5
R/O/L
Transmit Data FIFO Overrun. When set, this bit indicates that the CPU changed the value
of the Transmit Data Cell FIFO Write Pointer (2052h) to the value of the Transmit Data Cell
FIFO Read Pointer (2054h). When this event occurs, the MT90500 assumes that the CPU
is trying to write one more non-CBR cell than the FIFO can contain. Writing a ‘1’ over this
bit clears it.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT90500 | Multi-Channel ATM AAL1 SAR |
| MT90500AL | Multi-Channel ATM AAL1 SAR |
| MT90502 | Multi-Channel AAL2 SAR(多通道 ATM AAL2分段及重組設(shè)備（基于通訊總線的系統(tǒng)與ATM網(wǎng)絡(luò)的接口）) |
| MT90732AP | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| MT90732 | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT90500AL | 制造商:MITEL 制造商全稱(chēng):Mitel Networks Corporation 功能描述:Multi-Channel ATM AAL1 SAR |
| MT90500AL-ENG1 | 制造商:Mitel Networks Corporation 功能描述: |
| MT90502 | 制造商:ZARLINK 制造商全稱(chēng):Zarlink Semiconductor Inc 功能描述:Multi-Channel AAL2 SAR |
| MT90502_06 | 制造商:ZARLINK 制造商全稱(chēng):Zarlink Semiconductor Inc 功能描述:Multi-Channel AAL2 SAR |
| MT90502AG | 制造商:Rochester Electronics LLC 功能描述: 制造商:Zarlink Semiconductor Inc 功能描述: |
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