參數(shù)資料
型號： MT90500
廠商： Mitel Networks Corporation
英文描述： Multi-Channel ATM AAL1 SAR(多通道 ATM AAL1分段及重組設備（基于通訊總線的系統(tǒng)與ATM網(wǎng)絡的接口）)
中文描述： 多通道自動柜員機AAL1特區(qū)（多通道自動柜員機AAL1分段及重組設備（基于通訊總線的系統(tǒng)與空中交通管理網(wǎng)絡的接口））
文件頁數(shù)： 74/159頁
文件大?。?/td> 514K
代理商： MT90500
MT90500
74
4.6.2.2
Receive SRTS Operation
Note:
The following specification assumes that the MT90500 will perform the SRTS function with the use of
external logic as depicted in Figure 35 and Figure 36.
On the receive side, the MT90500 will generate a local RTS value (EXPECTED_SRTS) as depicted in
Figure 34 (and in a manner identical to that explained in detail in Section 4.6.2.1 for the transmit direction), and
will compare it with the received RTS code (RX_SRTS) from the incoming ATM stream. Up to five locally-
generated RTS values can be stored in a series of internal latches (a 5-deep FIFO).
The MT90500 internal comparator generates a 4-bit complement code that indicates the difference between
the locally generated RTS value and the incoming RTS value (remote - local). The value of this code ranges
from -8 (1000) to +7 (0111). The result of the comparison is then sent out via the SRTSDATA pin, with an
associated strobe output transmitted on SRTSENA. External user logic is necessary to monitor these
difference values, perform the clock adjustment and recover the original ST-BUS clock. If the difference values
increase, it is due to the fact that the remote bus is running faster than the local bus and therefore the local bus
frequency must be increased. Likewise, if the difference values are decreasing, it is because the remote bus is
running more slowly than the local bus, and thus the local bus must be slowed down.
Two 5-deep FIFOs are used to minimize the effect of cell delay variation in the transmission and reception
process and to minimize slips. For both the receive SRTS and the transmit SRTS processes, the FIFOs are
self-aligning: if an underrun or overrun is encountered, the FIFOs’ pointers are re-centered. These errors are
reported in the Clock Module General Status Register at 6082h.
4
Divide by x
4-bit counter
f
nx
MULTIPLE
LATCHES
clk
data_in
Figure 34 - Receive SRTS Operation
FNXI
enable
Byte Counter
CLKx1
period of the RTS
(one 8-cell cycle)
f
B
Gapping Control
f
B
Generator
SRTS Receive Divider Register
4
f
B
= f
S
/ 8 = service byte clock
Comparator
SRTSENA
enable
4
SRTSDATA
RX_SRTS
EXPECTED_
SRTS
RX_SAR
BLOCK
ATM Physical Layer
Network Clock
Internal to MT90500
Receive
ATM Cells
w/ CSI b
its
相關PDF資料
PDF描述
MT90500 Multi-Channel ATM AAL1 SAR
MT90500AL Multi-Channel ATM AAL1 SAR
MT90502 Multi-Channel AAL2 SAR(多通道 ATM AAL2分段及重組設備（基于通訊總線的系統(tǒng)與ATM網(wǎng)絡的接口）)
MT90732AP Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
MT90732 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
相關代理商/技術參數(shù)
參數(shù)描述
MT90500AL 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:Multi-Channel ATM AAL1 SAR
MT90500AL-ENG1 制造商:Mitel Networks Corporation 功能描述:
MT90502 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Multi-Channel AAL2 SAR
MT90502_06 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Multi-Channel AAL2 SAR
MT90502AG 制造商:Rochester Electronics LLC 功能描述: 制造商:Zarlink Semiconductor Inc 功能描述:
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