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參數(shù)資料
| 型號(hào)： | MT90500 |
| 廠(chǎng)商： | Mitel Networks Corporation |
| 英文描述： | Multi-Channel ATM AAL1 SAR(多通道 ATM AAL1分段及重組設(shè)備（基于通訊總線(xiàn)的系統(tǒng)與ATM網(wǎng)絡(luò)的接口）) |
| 中文描述： | 多通道自動(dòng)柜員機(jī)AAL1特區(qū)（多通道自動(dòng)柜員機(jī)AAL1分段及重組設(shè)備（基于通訊總線(xiàn)的系統(tǒng)與空中交通管理網(wǎng)絡(luò)的接口）） |
| 文件頁(yè)數(shù)： | 85/159頁(yè) |
| 文件大?。?/td> | 514K |
| 代理商： | MT90500 |
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MT90500
85
TIM_SERV
4
R/O
Timing Module Service Request. When ‘1’, indicates the Timing Recovery module requires
service (i.e. at least one Clock Recovery event bit (in register 6082h) and matching enable
bit (in register 6080h) are set. When this bit is ‘1’ and the TIM_INTE interrupt enable bit is
‘1’ in the MCR (Register 0000h), an external hardware interrupt is generated.
Reserved
6:5
R/0
Reserved. Undefined at reset.
SERVICE
7
R/O
‘1’ when any of bits<4:0> is set. Undefined at reset.
Reserved
15:8
R/O
Always read “0000_0000”
Table 14 - Window to External Memory Register - CPU
Address: 0030 (Hex)
Label: WTEMC
Reset Value: 0000 (Hex)
Label
Bit
Position
Type
Description
EXTMADD16
0
R/W
This bit represents address line A[16] for external memory access (CPU byte address).
This bit maps to MEM_ADD[14] (double-word address).
EXTMADD17
1
R/W
This bit represents address line A[17] for external memory access. This bit maps to
MEM_ADD[15] or bank_selection (32K addressing mode).
EXTMADD18
2
R/W
This bit represents address line A[18] for external memory access. This bit maps to
MEM_ADD[16] or bank_selection (64K addressing mode).
EXTMADD19
3
R/W
This bit represents address line A[19] for external memory access. This bit maps to
MEM_ADD[17] or bank_selection (128K addressing mode).
EXTMADD20
4
R/W
This bit represents address line A[20] for external memory access. This bit maps to
bank_selection (256K addressing mode).
Reserved
15:5
R/W
Reserved, must always be “0000_0000_000”.
This register is automatically used while a CPU access is performed.
Table 15 - Read Parity Register
Address: 0036 (Hex)
Label: RDPAR
Reset Value: 0000 (Hex)
Label
Bit Position
Type
Description
CPUPAR32
0
R/O
Bit 32 corresponds to the parity bit of the MS byte of the last odd word read from the
external memory by the CPU.
CPUPAR33
1
R/O
Bit 33 corresponds to the parity bit of the LS byte of the last odd word read from the
external memory by the CPU.
CPUPAR34
2
R/O
Bit 34 corresponds to the parity bit of the MS byte of the last even word read from the
external memory by the CPU.
CPUPAR35
3
R/O
Bit 35 corresponds to the parity bit of the LS byte of the last even word read from the
external memory by the CPU.
Reserved
7:4
R/O
Reserved.
Reserved
15:6
R/O
Reserved. Always read “0000_0000”.
Table 13 - Main Status Register
Address: 0002 (Hex)
Label: MSR
Reset Value: 00X0 (Hex)
Label
Bit Position
Type
Description
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT90500 | Multi-Channel ATM AAL1 SAR |
| MT90500AL | Multi-Channel ATM AAL1 SAR |
| MT90502 | Multi-Channel AAL2 SAR(多通道 ATM AAL2分段及重組設(shè)備（基于通訊總線(xiàn)的系統(tǒng)與ATM網(wǎng)絡(luò)的接口）) |
| MT90732AP | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| MT90732 | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT90500AL | 制造商:MITEL 制造商全稱(chēng):Mitel Networks Corporation 功能描述:Multi-Channel ATM AAL1 SAR |
| MT90500AL-ENG1 | 制造商:Mitel Networks Corporation 功能描述: |
| MT90502 | 制造商:ZARLINK 制造商全稱(chēng):Zarlink Semiconductor Inc 功能描述:Multi-Channel AAL2 SAR |
| MT90502_06 | 制造商:ZARLINK 制造商全稱(chēng):Zarlink Semiconductor Inc 功能描述:Multi-Channel AAL2 SAR |
| MT90502AG | 制造商:Rochester Electronics LLC 功能描述: 制造商:Zarlink Semiconductor Inc 功能描述: |
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