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參數(shù)資料
| 型號(hào)： | MT90500 |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | Multi-Channel ATM AAL1 SAR(多通道 ATM AAL1分段及重組設(shè)備（基于通訊總線的系統(tǒng)與ATM網(wǎng)絡(luò)的接口）) |
| 中文描述： | 多通道自動(dòng)柜員機(jī)AAL1特區(qū)（多通道自動(dòng)柜員機(jī)AAL1分段及重組設(shè)備（基于通訊總線的系統(tǒng)與空中交通管理網(wǎng)絡(luò)的接口）） |
| 文件頁(yè)數(shù)： | 59/159頁(yè) |
| 文件大小： | 514K |
| 代理商： | MT90500 |
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MT90500
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Three cell delay variation control fields must be initialized by the software: the “Minimum Lead”, “Maximum
Lead” and “Average Lead”. Each of these fields is concatenated with “00” (i.e. multiplied by 4) to have a range
from 0 to 1020. Before disassembling any cell, the RX_SAR verifies its write pointer’s validity with respect to
the Maximum and Minimum Lead fields, as discussed in Section 4.4.2.2.
The AAL1 byte is used by hardware to check the cell sequence number and therefore provide cell loss /
misinsertion detection. Before opening a VC, the user should write 00h into this field and then leave it for
hardware control.
The “S” bit (Structure un-initialized) serves to indicate that the structure has not been “run” yet. When the first
cell of a VCC arrives at the MT90500, the RX_SAR control structure is called by the lookup table for the first
time, and the 'S' bit is '0' as set by software. When the hardware loads the RX_SAR control structure from
memory, and sees that bit-15 in the 6th word is '0' (S is 0), this first cell is written starting at the location of the
Average Lead Pointer, which automatically sets up the buffer with average-lead of CDV tolerance.
The “BS” field indicates the size of the Receive Circular Buffers. The valid size ranges from 64 to 1024 bytes
and depends upon the amount of available memory and the cell delay variation (CDV) in the network. Note that
all channels arriving on the same VC must have the same CDV and therefore their RX Circular Buffers will all
be the same size.
The “RX_SAR Write Pointer” is initialized to zero by software and used only by the hardware.
Unlike the Transmit Control Structures, there is no difference in the configuration of the RX_SAR Control Struc-
tures for the various cell types. In fact, the only thing which differentiates the control structures for different
AALs is the AS field. In particular, this field is set to “00” for CBR-AAL0 and CBR-AAL5 cells (because CBR-
AAL5 is really just a special case of CBR-AAL0), or “10” for AAL1. AAL1 cells which are carrying SRTS information
are identified by an AS setting of “11”.
As with the Transmit Control Structures, all RX_SAR Control Structures must start on 16-byte boundaries and
must never cross 256-byte boundaries.
4.4.2.2
RX_SAR Error Counter and Interrupt Sources
The RX_SAR has three 16-bit error counters, and three error structure ID registers for error monitoring. When
receiving a cell, any of the following errors can be detected: a write overrun error, a write underrun error, an
AAL1 byte parity error, an AAL1 CRC error, a sequence number error, a P-byte parity error, or a P-byte out of
range error. A counter and ID register are used to monitor each of the two write slip-type errors (3022h and
3020h for Underrun events; 3032h and 3030h for Overrun events). The other five types of errors share common
counter (3012h) and event ID (3010h) registers. Five bits in the RX_SAR Control Register (3000h) allow the
control software to choose which error events affect the count and ID registers. If more than one error count
enable is active, the counter will add all occurrences of the various errors. The ID register points to the
RX_SAR Control Structure which experienced the last recorded error. All of the errors should be self-
explanatory, except for the P-byte out of range error. This error occurs when the P-byte’s value implies that a
hyper-channel contains more channels than indicated by the RX_SAR Control Structure.
NOTE that received cells with AAL1 errors (e.g. sequence numbers, AAL1-byte parity, AAL1-byte CRC, P-byte
parity and P-byte CRC) are NOT discarded. The dropping of such cells is optional in the AF-VTOA-0078 CES-
IS V2.0 specification. The cell contents are passed to the AAL1 reassembly process on the basis that
corruption of the AAL1-byte may or may not imply corruption of the TDM contents, and that TDM channels are
generally relatively tolerant of noise, and that using these cells will help to maintain timing.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT90500 | Multi-Channel ATM AAL1 SAR |
| MT90500AL | Multi-Channel ATM AAL1 SAR |
| MT90502 | Multi-Channel AAL2 SAR(多通道 ATM AAL2分段及重組設(shè)備（基于通訊總線的系統(tǒng)與ATM網(wǎng)絡(luò)的接口）) |
| MT90732AP | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| MT90732 | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT90500AL | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:Multi-Channel ATM AAL1 SAR |
| MT90500AL-ENG1 | 制造商:Mitel Networks Corporation 功能描述: |
| MT90502 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Multi-Channel AAL2 SAR |
| MT90502_06 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Multi-Channel AAL2 SAR |
| MT90502AG | 制造商:Rochester Electronics LLC 功能描述: 制造商:Zarlink Semiconductor Inc 功能描述: |
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