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參數(shù)資料
| 型號(hào)： | MT90500 |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | Multi-Channel ATM AAL1 SAR(多通道 ATM AAL1分段及重組設(shè)備（基于通訊總線的系統(tǒng)與ATM網(wǎng)絡(luò)的接口）) |
| 中文描述： | 多通道自動(dòng)柜員機(jī)AAL1特區(qū)（多通道自動(dòng)柜員機(jī)AAL1分段及重組設(shè)備（基于通訊總線的系統(tǒng)與空中交通管理網(wǎng)絡(luò)的接口）） |
| 文件頁(yè)數(shù)： | 16/159頁(yè) |
| 文件大?。?/td> | 514K |
| 代理商： | MT90500 |
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MT90500
16
Supports partially-filled cells (AAL1, CBR-AAL5, and CBR-AAL0).
User-defined, per-VC, Cell Delay Variation tolerance: 8 to 128 ms buffer size (up to 64 ms CDV).
Handles TDM channels at 64 kbps granularity.
Each individual VC can be composed of N x 64 kbps wideband channels (N = 1, 2, ..., 122).
Flexible aggregation capability (N x 64 kbps) maintains frame integrity, while allowing any combi-
nation of 64 kbps channels (DS0 grooming).
Supports “multi-casting” of one TDM DS0 input channel to multiple Transmit ATM VCs, and of one
Receive ATM DS0 to multiple TDM outputs.
A VC can contain any combination of TDM channels from any combination of TDM streams
(Nx64) and maintain frame integrity for those channels.
Supports several 8 kHz synchronisation operations: synchronized to external 8 kHz reference,
synchronized to network clock, and synchronized to timing derived from an ATM VC (including
ITU-T I.363.1 Adaptive and SRTS clock recovery mechanisms).
2.4
External Memory Interface
To implement SAR functions and buffers, the MT90500 device uses external Synchronous SRAM.
External Synchronous SRAM size is chosen by user, and depends on Cell Delay Variation (CDV)
and the number of simultaneous 64 kbps channels handled. The amount of Synchronous SRAM is
scalable to suit the application, and may range from 128 Kbytes to 2,048 Kbytes.
2.5
UTOPIA Interface and Multiplexer
UTOPIA Level 1 compatible 8-bit bus, running at up to 25 Mbyte/s, for connection to PHY devices
with data throughput of up to 155 Mbps.
Transmit multiplexer mixes cells from TX_SAR and Secondary UTOPIA port, supporting another
MT90500, and/or an external SAR device (e.g. AAL5) connected to a single PHY device.
Programmable multiplexer priority gives internally generated AAL1 cells equal, or higher, priority
than cells coming from Secondary UTOPIA port.
Supports non-CBR data cells and OAM cells destined for microprocessor with Receive and Trans-
mit Data Cell FIFOs.
Flexible receive cell handling: AAL1 (as well as CBR-AAL0 and CBR-AAL5) cells are sent to the
TDM port; data cells (non-CBR data and OAM cells) are sent to the Receive Data Cell FIFO; cells
with unrecognized VCs may be queued or ignored.
Cell reception based on look-up-table allows flexible VC assignment for CBR VCs (allows non-
contiguous VC assignment).
Programmable VPI/VCI Match and Mask filtering reduces unnecessary look-up-table accesses.
2.6
Microprocessor Interface
16-bit microprocessor port, configurable to Motorola or Intel timing.
Programmable interrupts for control and statistics.
Allows access to internal registers for initialization, control, and statistics.
Allows access to external SSRAM for initialization, control, and observation.
2.7
Miscellaneous
Master clock rate up to 60 MHz.
Dual rails (3.3V for power minimization, 5V for standard I/O).
Loopback function provided at the TDM interface.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT90500 | Multi-Channel ATM AAL1 SAR |
| MT90500AL | Multi-Channel ATM AAL1 SAR |
| MT90502 | Multi-Channel AAL2 SAR(多通道 ATM AAL2分段及重組設(shè)備（基于通訊總線的系統(tǒng)與ATM網(wǎng)絡(luò)的接口）) |
| MT90732AP | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| MT90732 | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT90500AL | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:Multi-Channel ATM AAL1 SAR |
| MT90500AL-ENG1 | 制造商:Mitel Networks Corporation 功能描述: |
| MT90502 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Multi-Channel AAL2 SAR |
| MT90502_06 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Multi-Channel AAL2 SAR |
| MT90502AG | 制造商:Rochester Electronics LLC 功能描述: 制造商:Zarlink Semiconductor Inc 功能描述: |
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