參數(shù)資料
型號： MT90500
廠商： Mitel Networks Corporation
英文描述： Multi-Channel ATM AAL1 SAR(多通道 ATM AAL1分段及重組設(shè)備（基于通訊總線的系統(tǒng)與ATM網(wǎng)絡(luò)的接口）)
中文描述： 多通道自動柜員機AAL1特區(qū)（多通道自動柜員機AAL1分段及重組設(shè)備（基于通訊總線的系統(tǒng)與空中交通管理網(wǎng)絡(luò)的接口））
文件頁數(shù)： 29/159頁
文件大小： 514K
代理商： MT90500
MT90500
29
The CLKx2 signal can be selected as single-ended or differential. (Differential CLKx2 allows com-
patibility with the H-MVIP bus.) In TDM Timing Slave, the CLKx2 signal can be input on the CLKx2
pin, or the differential CLKx2PI and CLKx2NI pins. This selection is made with CLKTYPE in the
TDM Bus Type Register at address 6010h. In TDM Timing Master, the CLKx2 signal is output on
the CLKx2/CLKx2PO pin, and an inverted clock is available on the CLKx2NO pin.
The MT90500 supports the following TDM timing modes:
TDM Timing Bus Slave - CLKx2 Reference
(CLKMASTER = ‘0’ in TDM Bus Type Register at 6010h)
In this mode, the MT90500 is configured as a TDM Timing Slave and all internal TDM timing is synchronized to
the TDM clock inputs: CLKx2, CLKx1, and FSYNC. The following sub-modes are also selectable:
The CLKx1 can be an input at the CLKx1 pin, or it can be derived internally from CLKx2. This is
controlled by TCLKSYN (address 6010h). If the CLKx1 pin is not used as an input in TDM Slave
mode, it remains high-impedance.
TDM Timing Slave operation takes its 8 kHz framing from the FSYNC input pin, which would usu-
ally be driven by the TDM bus. To support other implementations, the REF8KCLK output remains
active in TDM Slave mode. An 8 kHz reference output can be made available at REF8KCLK,
selectable from the EX_8KA input, the SEC8K pin, or one of the internal dividers. In addition, the
FREERUN output can be used to monitor the presence of REF8KCLK.
Main TDM
Bus Timing
and
Clock
Generation
Logic
0
1
2
3
External
PLL
(Optional)
CLKx2
FSYNC
EX_8KA
MCLK
RXVCLK
REF8KCLK
0
1
PLLCLK
SEC8K
0
1
Figure 3 - TDM Clock Selection and Generation Logic
CLKx2
CLKx1
FSYNC
Master/Slave
Clock Absent
Detection
Logic
SEC8KEN
FREERUN
Local TDM
Bus
Clock
Generation
Logic
LOCx2
LOCx1
LSYNC
L
M
MT9041 or
other PLL
CLK16
(16.384 MHz)
0
1
SEC8K_INT
EX_8KA_INT
REFSEL<1:0>
DIVCLK_SRC
BEPLL
SEC8KSEL
Adaptive
Clock
Recovery
ATM Cells
Divide by 2
to 16384
Divide by
1,2,4,or 8
FSYNC
EX_8KA_INT
REF8KCLK
Detection
Logic
External CPU Bus
I
FS_INT
FS_INT
DIV1...8
PHLEN
Square
Square
SEC8K_SQ
EX_8KA_SQ
All control bits shown are in Master Clock Generation Control Register (6090h).
1 0
1
0
CLKx1
MT90500
SRTS Clock
Recovery
FNXI
SRTS
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MT90500AL 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:Multi-Channel ATM AAL1 SAR
MT90500AL-ENG1 制造商:Mitel Networks Corporation 功能描述:
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MT90502_06 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Multi-Channel AAL2 SAR
MT90502AG 制造商:Rochester Electronics LLC 功能描述: 制造商:Zarlink Semiconductor Inc 功能描述:
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