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參數(shù)資料
| 型號(hào)： | MT90500 |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | Multi-Channel ATM AAL1 SAR(多通道 ATM AAL1分段及重組設(shè)備（基于通訊總線的系統(tǒng)與ATM網(wǎng)絡(luò)的接口）) |
| 中文描述： | 多通道自動(dòng)柜員機(jī)AAL1特區(qū)（多通道自動(dòng)柜員機(jī)AAL1分段及重組設(shè)備（基于通訊總線的系統(tǒng)與空中交通管理網(wǎng)絡(luò)的接口）） |
| 文件頁(yè)數(shù)： | 15/159頁(yè) |
| 文件大?。?/td> | 514K |
| 代理商： | MT90500 |
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MT90500
15
2.
Features
2.1
General
The MT90500 device external interfaces are:
TDM (Time Division Multiplexed) bus composed of 16 serial streams running at up to 8.192 Mbps,
plus related clocks and control signals, configurable by software. This interface also includes vari-
ous signals for TDM clock signal generation. This bus carries telecom or other data in N x 64 kbps
streams.
Local serial TDM bus interface (a TDM input pin, a TDM output pin, and clocks).
A primary UTOPIA bus running at up to 25 MHz, suitable for connection to a 25 Mbps or 155 Mbps
PHY device.
A secondary UTOPIA bus, for connection of an optional external SAR (e.g. data) device running at
up to 25 MHz. In this case, the MT90500 device emulates a PHY device for the external SAR.
A synchronous 36-bit wide memory interface running at up to 60 MHz.
A 16-bit microprocessor interface used for device configuration, status, and control.
Signals for general clocking, reset, and JTAG boundary-scan.
2.2
Serial TDM Bus
Compatible with ST-BUS, MVIP, H-MVIP, IDL, and SCSA interfaces.
Provides 16 bidirectional serial streams that can operate at TDM data rates of 2.048, 4.096 or
8.192 Mbps for up to 2048 TDM 64 kbps channels (1024 bidirectional DS0 channels: supports 32
E1 framers, or 42 T1 framers, or 10 J2 framers).
Serial TDM bus clocking schemes: TDM timing bus slave (MT90500 slaved to TDM bus), TDM tim-
ing bus master (MT90500 drives clocks onto TDM bus - freerun, or synchronized to 8 kHz refer-
ence) and TDM bus master-alternate (MT90500 slaved to TDM bus, but ready to switch to 8 kHz
reference).
Additional Local TDM Bus interface (2.048 Mbps) allows local TDM devices to access the main
TDM bus.
2.3
CBR ATM Cell Processor
Independent Segmentation and Reassembly blocks for receive and transmit (RX_SAR and
TX_SAR) support CBR (Constant Bit Rate) transport of half- or full-duplex TDM channels.
Compatible with “Structured Data Transfer (SDT) services” as per ANSI T1.630 standard for 1 to
122 TDM channels per VC.
Compatible with ITU-T I.363.1 “circuit transport” of 8 kHz structured data using Structured Data
Transfer (SDT) for 1 to 96 TDM channels per VC (using buffer-fill level monitoring).
Compatible with ITU-T I.363.1 “voiceband signal transport.”
Compatible with AF-VTOA-0078.000 “N x 64 Basic Service” (non-CAS) Circuit Emulation (using
buffer-level monitoring, rather than lost cell insertion).
Compatible with AF-VTOA-0078.000 for SDT of partially-filled AAL1 cells with N-channel struc-
tures (where N does not exceed the value of the partial-fill).
AAL1 SAR-PDU Header processing (AAL1 Sequence Number checking).
Supports up to 1024 bidirectional VCs (virtual circuits) simultaneously.
Supports up to 1024 transmit TDM channels and 1024 receive TDM channels simultaneously.
Supports CBR-AAL0 (48 byte cell payload).
Supports CBR-AAL5 as per AF-VTOA-0083.000, also supports Nx64 trunking over CBR-AAL5.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT90500 | Multi-Channel ATM AAL1 SAR |
| MT90500AL | Multi-Channel ATM AAL1 SAR |
| MT90502 | Multi-Channel AAL2 SAR(多通道 ATM AAL2分段及重組設(shè)備（基于通訊總線的系統(tǒng)與ATM網(wǎng)絡(luò)的接口）) |
| MT90732AP | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| MT90732 | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT90500AL | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:Multi-Channel ATM AAL1 SAR |
| MT90500AL-ENG1 | 制造商:Mitel Networks Corporation 功能描述: |
| MT90502 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Multi-Channel AAL2 SAR |
| MT90502_06 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Multi-Channel AAL2 SAR |
| MT90502AG | 制造商:Rochester Electronics LLC 功能描述: 制造商:Zarlink Semiconductor Inc 功能描述: |
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