參數(shù)資料
型號(hào)： MT57W4MH9CF-6
元件分類： SRAM
英文描述： 4M X 9 DDR SRAM, 0.5 ns, PBGA165
封裝： 15 X 17 MM, 1 MM PITCH, FBGA-165
文件頁(yè)數(shù)： 5/29頁(yè)
文件大?。?/td> 344K
代理商： MT57W4MH9CF-6
4 MEG x 8, 4 MEG x 9, 2 MEG x 18, 1 MEG x 36
1.8V VDD, HSTL, DDR SIO SRAM
ADVANCE
36Mb: 1.8V VDD, HSTL, QDRB2 SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT57W2MH18C_B.fm – Rev. B, Pub. 2/03
13
2003 Micron Technology, Inc.
NOTE:
1. X means “Don’t Care.” H means logic HIGH. L means logic LOW.
means rising edge; means falling edge.
2. Data inputs are registered at K and K# rising edges. Data outputs are delivered at C and C# rising edges, except if C
and C# are HIGH, then data outputs are delivered at K and K# rising edges.
3. LD# and R/W# must meet setup/hold times around the rising edge (LOW to HIGH) of K and are registered at the ris-
ing edge of K.
4. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.
5. Refer to state diagram and timing diagrams for clarification.
6. It is recommended that K = K# = C = C# when clock is stopped. This is not essential but permits most rapid restart by
overcoming transmission line charging symmetrically.
7. Assumes a WRITE cycle was initiated. BW0# and BW1# can be altered for any portion of the BURST WRITE operation
provided that the setup and hold requirements are satisfied.
8. This table illustrates the operation for the x18 devices. The x36 device operation is similar, except for the addition of
BW2# (controls D18:D26) and BW3# (controls D27:D35). The x9 device operation is similar, except that BW1# and
D9:D17 are not used. The x8 device operation is similar, except that NW0# controls D0:D3 and NW1# controls D4:D7.
Table 7:
Truth Table
Notes 1-6
OPERATION
K
LD#
R/W#
D or Q
WRITE Cycle:
Load address, input write data on
consecutive K and K# rising edges
L
HX
L
DA(A0) at
K(t)
Q = High-Z
DA(A0 + 1) at
K
#(t + 1)
Q = High-Z
READ Cycle:
Load address, output data on
consecutive C and C# rising edges
L
HL
H
QA(A0)
at
C#(t)
QA(A0 + 1)
at
C(t + 1)
NOP: No operation
L
HH
X
D = X
Q = High-Z
D = X
Q = High-Z
STANDBY: Clock stopped
Stopped
X
Previous
State
Previous
State
Table 8:
BYTE WRITE Operation
Notes 7, 8
OPERATION
K
K#
BW0#
BW1#
WRITE D0:17 at K rising edge
L
H0
0
WRITE D0:17 at K# rising edge
L
H0
0
WRITE D0:8 at K rising edge
L
H0
1
WRITE D0:8 at K# rising edge
L
H0
1
WRITE D9:17 at K rising edge
L
H1
0
WRITE D9:17 at K# rising edge
L
H1
0
WRITE nothing at K rising edge
L
H1
1
WRITE nothing at K# rising edge
L
H1
1
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