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參數(shù)資料
| 型號： | MT57W4MH9CF-6 |
| 元件分類： | SRAM |
| 英文描述： | 4M X 9 DDR SRAM, 0.5 ns, PBGA165 |
| 封裝： | 15 X 17 MM, 1 MM PITCH, FBGA-165 |
| 文件頁數(shù)： | 25/29頁 |
| 文件大小： | 344K |
| 代理商： | MT57W4MH9CF-6 |
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4 MEG x 8, 4 MEG x 9, 2 MEG x 18, 1 MEG x 36
1.8V VDD, HSTL, DDR SIO SRAM
ADVANCE
36Mb: 1.8V VDD, HSTL, QDRB2 SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT57W2MH18C_B.fm – Rev. B, Pub. 2/03
5
2003 Micron Technology, Inc.
Figure 3: Application Example
NOTE:
1. In this approach, the second clock pair drives the C and C# clocks but is delayed such that return data meets setup
and hold times at the bus master.
2. Consult Micron Technical Notes for more thorough discussions of clocking schemes.
3. Data capture is possible using only one of the two signals. CQ and CQ# clocks are optional use outputs.
4. For high frequency applications (200 MHz and faster) the CQ and CQ# clocks (for data capture) are recommended
over the C and C# clocks (for data alignment). The C and C# clocks are optional use inputs.
Vt
Vt = VREF
Vt
CC#
D
SA
K
CC#
D
SA
K
BUS
MASTER
(CPU
or
ASIC)
DATA IN
DATA OUT
Address
R/W#
LD#
BW#
SRAM 1 Input CQ
SRAM 1 Input CQ#
SRAM 4 Input CQ
SRAM 4 Input CQ#
Return CLK
Source CLK
Return CLK#
Source CLK#
R = 50
R/W
#
B
W
0
#
B
W
1
#
B
W
0
#
B
W
1
#
Vt
R
LD
#
R/W
#
LD
#
CQ
CQ#
K#
ZQ
Q
SRAM 1
SRAM 2
R = 250
CQ
CQ#
K#
ZQ
Q
R = 250
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT57W512H36BF-7.5 | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Micron Technology Inc 功能描述: |
| MT57W512H36JF-4 | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Micron Technology Inc 功能描述: |
| MT57W512H36JF-5 | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Micron Technology Inc 功能描述: |
| MT57W512H36JF-6 | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Micron Technology Inc 功能描述: |
| MT57W512H36JF-7.5 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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