
4 MEG x 8, 4 MEG x 9, 2 MEG x 18, 1 MEG x 36
1.8V VDD, HSTL, DDR SIO SRAM
ADVANCE
36Mb: 1.8V VDD, HSTL, QDRB2 SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT57W2MH18C_B.fm – Rev. B, Pub. 2/03
29
2003 Micron Technology, Inc.
Document Revision History
Rev. G, Pub 2/03...............................................................................................................................................................2/03
Added definitive notes to Figure
3 Added definitive note to Table
9 Updated AC Timing specifications with new codevelopment values
Added definitive note concerning bit# 64 to Table 19
Removed Errata specifications
Updated AC timing values with new codevelopment values
Removed all references of device not being 1149.1 JTAG compliant
Added definitive note concerning SRAM (DQ) I/O balls used for JTAG DC values and timing
Changed process information in header to die revision indicator
Updated Thermal Resistance Values to Table 12:
CI = 4.5 TYP; 5.5 MAX
CO = 6 TYP; 7 MAX
CCK = 5.5 TYP; 6.5 MAX
Updated Thermal Resistance values to Table 12:
JA = 19.4 TYP
JC = 1.0 TYP
JB = 9.6 TYP
Added TJ +95°C to Table 13
Modified Figure 2 regarding depth, configuration, and byte controls
Added definitive notes regarding I/O behavior during JTAG operation
Added definitive notes regarding IDD test conditions for read to write ratio
Removed note regarding AC derating information for full I/O range
Remove references to JTAG scan chain logic levels being at logic zero for NC pins in Tables 5 and 19
Revised ball description for NC balls:
These balls are internally connected to the die, but have no function and may be left not connected to the
board to minimize ball count.
Rev. A, Pub. 9/02 ..............................................................................................................................................................9/02
New ADVANCE data sheet