參數(shù)資料
型號(hào): MT57W4MH9CF-6
元件分類(lèi): SRAM
英文描述: 4M X 9 DDR SRAM, 0.5 ns, PBGA165
封裝: 15 X 17 MM, 1 MM PITCH, FBGA-165
文件頁(yè)數(shù): 13/29頁(yè)
文件大小: 344K
代理商: MT57W4MH9CF-6
4 MEG x 8, 4 MEG x 9, 2 MEG x 18, 1 MEG x 36
1.8V VDD, HSTL, DDR SIO SRAM
ADVANCE
36Mb: 1.8V VDD, HSTL, QDRB2 SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT57W2MH18C_B.fm – Rev. B, Pub. 2/03
20
2003 Micron Technology, Inc.
Figure 6:
READ/WRITE Timing
NOTE:
1. Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, i.e.,
A0 + 1.
2. Outputs are disabled (High-Z) one clock cycle after a NOP.
3. In this example, if address A3 = A4, then data Q40 = D30 and Q41 = D31. Write data is forwarded immediately as
read results.
K
1
23456
78
K#
LD#
R/W#
A
Q
D
C
C#
READ
(burst of 2)
READ
(burst of 2)
READ
(burst of 2)
(Note 2)
(Note 1)
(Note 3)
WRITE
(burst of 2)
WRITE
(burst of 2)
Q40
tKHKL
tKHK#H
tKHCH
tCHQV
tKLKH
tKHKH
t
tKHIX
tAVKH tKHAX
tDVKH
tKHDX
tKHCH
NOP
tDVKH
tKHDX
DON’T CARE
UNDEFINED
tCHQX1
tCHQX
tCHQZ
IVKH
tKHKL
tKHK#H
tKLKH
tKHKH
A0
Q00
Q11
Q01
Q101
Qx2
tCHQV
tCQHQV
tCHQX
A1
A2
A3
A4
Q41
D20
D21
D30
D31
NOP
CQ
CQ#
tCHCQV
tCHCQX
tCHCQV
tCHCQX
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