參數(shù)資料
型號(hào)： MT57W4MH9CF-6
元件分類： SRAM
英文描述： 4M X 9 DDR SRAM, 0.5 ns, PBGA165
封裝： 15 X 17 MM, 1 MM PITCH, FBGA-165
文件頁(yè)數(shù)： 18/29頁(yè)
文件大?。?/td> 344K
代理商： MT57W4MH9CF-6
4 MEG x 8, 4 MEG x 9, 2 MEG x 18, 1 MEG x 36
1.8V VDD, HSTL, DDR SIO SRAM
ADVANCE
36Mb: 1.8V VDD, HSTL, QDRB2 SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT57W2MH18C_B.fm – Rev. B, Pub. 2/03
25
2003 Micron Technology, Inc.
TAP AC Test Conditions
Input pulse levels ....................................... VSS to 1.8V
Input rise and fall times .........................................1ns
Input timing reference levels .............................. 0.9V
Output reference levels ........................................ 0.9V
Test load termination supply voltage.................. 0.9V
Figure 10:
TAP AC Output Load Equivalent
NOTE:
1. All voltages referenced to VSS (GND)
.
2. Overshoot: VIH (AC)
VDD + 0.7V for t tKHKH/2
Undershoot: VIL (AC)
-0.5V for t tKHKH/2
Power-up:
VIH
+1.9V and VDD +1.7V for t 200ms
During normal operation, VDDQ must not exceed VDD. Control input signals (LD#, R/W#, etc.) may not have pulse
widths less than tKHKL (MIN) or operate at frequencies exceeding fKF (MAX).
3. This table defines DC values for TAP control and data balls only. The DQ SRAM balls used in JTAG operation will have
TDO
0.9V
20pF
Z = 50
O
50
Table 16:
TAP DC Electrical Characteristics and Operating Conditions
Note 3; 0°C
TA +70°C; VDD = 1.8V ±0.1V unless otherwise noted
DESCRIPTION
CONDITIONS
SYMBOL
MIN
MAX
UNITS
NOTES
Input High (Logic 1) Voltage
VIH
1.3
VDD + 0.3
V
Input Low (Logic 0) Voltage
VIL
-0.3
0.5
V
Input Leakage Current
0V
VIN VDD
ILI
-5.0
5.0
A
Output Leakage Current
Output(s) disabled,
0V
VIN VDD
ILO
-5.0
5.0
A
Output Low Voltage
IOLC = 100A
VOL1
0.2
V
Output Low Voltage
IOLT = 2mA
VOL2
0.4
V
Output High Voltage
|IOHC| = 100A
VOH1
1.6
V
Output High Voltage
|IOHT| = 2mA
VOH2
1.4
V
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