參數(shù)資料
型號(hào): MT57W4MH9CF-6
元件分類: SRAM
英文描述: 4M X 9 DDR SRAM, 0.5 ns, PBGA165
封裝: 15 X 17 MM, 1 MM PITCH, FBGA-165
文件頁(yè)數(shù): 10/29頁(yè)
文件大小: 344K
代理商: MT57W4MH9CF-6
4 MEG x 8, 4 MEG x 9, 2 MEG x 18, 1 MEG x 36
1.8V VDD, HSTL, DDR SIO SRAM
ADVANCE
36Mb: 1.8V VDD, HSTL, QDRB2 SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT57W2MH18C_B.fm – Rev. B, Pub. 2/03
18
2003 Micron Technology, Inc.
Notes
1. Outputs
are
impedance-controlled.
|IOH|
=
(VDDQ/2)/(RQ/5) for values of 175
W RQ 350W .
2. Outputs are impedance-controlled. IOL = (VDDQ/
2)/(RQ/5) for values of 175
W RQ 350W .
3. All voltages referenced to VSS (GND).
4. Overshoot: VIH(AC)
VDD + 0.7V for t tKHKH/2
Undershoot: VIL(AC)
-0.5V for t tKHKH/2
Power-up:
VIH
VDDQ + 0.3V and VDD 1.7V
and VDDQ
1.4V for t 200ms
During normal operation, VDDQ must not exceed
VDD. Control signals may not have pulse widths
less than tKHKL (MIN) or operate at cycle rates
less than tKHKH (MIN).
5. AC load current is higher than the shown DC val-
ues. AC I/O curves are available upon request.
6. HSTL outputs meet JEDEC HSTL Class I and Class
II standards.
7. The nominal value of VDDQ may be set within the
range of 1.5V to 1.8V DC, and the variation of
VDDQ must be limited to ±0.1V DC.
8. To maintain a valid level, the transitioning edge of
the input must:
a. Sustain a constant slew rate from the current AC
level through the target AC level, VIL(AC) or
VIH(AC).
b. Reach at least the target AC level.
c. After the AC target level is reached, continue to
maintain at least the target DC level, VIL(DC) or
VIH(DC).
9. IDD is specified with no output current. IDD is lin-
ear with frequency. Typical value is measured at
6ns cycle time.
10. Typical values are measured at VDD = 1.8V, VDDQ =
1.5V, and temperature = 25°C.
11. NOP currents are valid when entering NOP after
all pending READ and WRITE cycles are com-
pleted.
12. Average I/O current and power is provided for
informational purposes only and is not tested.
Calculation assumes that all outputs are loaded
with CL (in farads), f = input clock frequency, half
of outputs toggle at each transition (n = 18 for the
x36), CO = 6pF, VDDQ = 1.5V and uses the equa-
tions: Average I/O Power as dissipated by the
SRAM is: P = 0.5 × n × f × VDDQ2 x (CL + 2CO).
Average IDDQ = n × f × VDDQ x (CL + CO).
13. This parameter is sampled.
14. Average thermal resistance between the die and
the case top surface per MIL SPEC 883 Method
1012.1.
15. Junction temperature is a function of total device
power dissipation and device mounting environ-
ment. Measured per SEMI G38-87.
16. This is a synchronous device. All addresses, data,
and control lines must meet the specified setup
and hold times for all latching clock edges.
17. Test conditions as specified with the output load-
ing as shown in Figure 5 unless otherwise noted.
18. Control input signals may not be operated with
pulse widths less than tKHKL (MIN).
19. If C and C# are tied HIGH, then K and K# become
the references for C and C# timing parameters.
20. The device will operate at clock frequencies
slower than tKHKH (MAX). See Micron Technical
Note TN-54-02 for more information.
21. Clock phase jitter is the variance from clock rising
edge to the next expected clock rising edge.
22. VDD slew rate must be less than 0.1V DC per 50ns
for DLL lock retention. DLL lock time begins once
VDD and input clock are stable.
23. Echo clock is tightly controlled to data valid/data
hold. By design, there is a ±0.1ns variation from
echo clock to data. The data sheet parameters
reflect tester guardbands and test setup varia-
tions.
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