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參數(shù)資料
| 型號： | MQ83C154XXX-16/883D |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 16 MHz, MICROCONTROLLER, CQFP44 |
| 文件頁數(shù)： | 33/204頁 |
| 文件大小： | 5687K |
| 代理商： | MQ83C154XXX-16/883D |
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128
ATtiny40 [DATASHEET]
8263B–AVR–01/2013
first completes its high period (DEVICE1) forces the clock line low and the procedure are then repeated. The result
of this is that the device with the shortest clock period determines the high period while the low period of the clock
is determined by the longest clock period.
17.3.10
Compatibility with SMBus
As with any other I2C-compliant interface there are known compatibility issues the designer should be aware of
before connecting a TWI device to SMBus devices. For use in SMBus environments, the following should be
noted:
All I/O pins of an AVR, including those of the two-wire interface, have protection diodes to both supply voltage
and ground. See Figure 10-1 on page 42. This is in contradiction to the requirements of the SMBus
specifications. As a result, supply voltage mustn’t be removed from the AVR or the protection diodes will pull the
bus lines down. Power down and sleep modes is not a problem, provided supply voltages remain.
The data hold time of the TWI is lower than specified for SMBus. The TWSHE bit of TWSCRA can be used to
increase the hold time. See “TWSCRA – TWI Slave Control Register A” on page 130.
SMBus has a low speed limit, while I2C hasn’t. As a master in an SMBus environment, the AVR must make sure
bus speed does not drop below specifications, since lower bus speeds trigger timeouts in SMBus slaves. If the
AVR is configured a slave there is a possibility of a bus lockup, since the TWI module doesn't identify timeouts.
17.4
TWI Slave Operation
The TWI slave is byte-oriented with optional interrupts after each byte. There are separate interrupt flags for Data
Interrupt and Address/Stop Interrupt. Interrupt flags can be set to trigger the TWI interrupt, or be used for polled
operation. There are dedicated status flags for indicating ACK/NACK received, clock hold, collision, bus error and
read/write direction.
When an interrupt flag is set, the SCL line is forced low. This will give the slave time to respond or handle any data,
and will in most cases require software interaction. Figure 17-11. shows the TWI slave operation. The diamond
shapes symbols (SW) indicate where software interaction is required.
Figure 17-11. TWI Slave Operation
The number of interrupts generated is kept at a minimum by automatic handling of most conditions. Quick Com-
mand can be enabled to auto trigger operations and reduce software complexity.
Promiscuous Mode can be enabled to allow the slave to respond to all received addresses.
17.4.1
Receiving Address Packets
When the TWI slave is properly configured, it will wait for a START condition to be detected. When this happens,
the successive address byte will be received and checked by the address match logic, and the slave will ACK the
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