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Figure 17-7. Combined Transaction
17.3.7
Clock and Clock Stretching
All devices connected to the bus are allowed to stretch the low period of the clock to slow down the overall clock
frequency or to insert wait states while processing data. A device that needs to stretch the clock can do this by
holding/forcing the SCL line low after it detects a low level on the line.
Three types of clock stretching can be defined as shown in
Figure 17-8.Figure 17-8. Clock Stretching
If the device is in a sleep mode and a START condition is detected the clock is stretched during the wake-up period
for the device.
A slave device can slow down the bus frequency by stretching the clock periodically on a bit level. This allows the
slave to run at a lower system clock frequency. However, the overall performance of the bus will be reduced
accordingly. Both the master and slave device can randomly stretch the clock on a byte level basis before and after
the ACK/NACK bit. This provides time to process incoming or prepare outgoing data, or performing other time crit-
ical tasks.
In the case where the slave is stretching the clock the master will be forced into a wait-state until the slave is ready
and vice versa.
17.3.8
Arbitration
A master can only start a bus transaction if it has detected that the bus is idle. As the TWI bus is a multi master
bus, it is possible that two devices initiate a transaction at the same time. This results in multiple masters owning
the bus simultaneously. This is solved using an arbitration scheme where the master loses control of the bus if it is
not able to transmit a high level on the SDA line. The masters who lose arbitration must then wait until the bus
becomes idle (i.e. wait for a STOP condition) before attempting to reacquire bus ownership. Slave devices are not
involved in the arbitration procedure.