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| 型號(hào)： | MQ83C154XXX-16/883D |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 16 MHz, MICROCONTROLLER, CQFP44 |
| 文件頁(yè)數(shù)： | 32/204頁(yè) |
| 文件大?。?/td> | 5687K |
| 代理商： | MQ83C154XXX-16/883D |
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127
ATtiny40 [DATASHEET]
8263B–AVR–01/2013
Figure 17-9. TWI Arbitration
Figure 17-9 shows an example where two TWI masters are contending for bus ownership. Both devices are able to
issue a START condition, but DEVICE1 loses arbitration when attempting to transmit a high level (bit 5) while
DEVICE2 is transmitting a low level.
Arbitration between a repeated START condition and a data bit, a STOP condition and a data bit, or a repeated
START condition and STOP condition are not allowed and will require special handling by software.
17.3.9
Synchronization
A clock synchronization algorithm is necessary for solving situations where more than one master is trying to con-
trol the SCL line at the same time. The algorithm is based on the same principles used for clock stretching
previously described. Figure 17-10 shows an example where two masters are competing for the control over the
bus clock. The SCL line is the wired-AND result of the two masters clock outputs.
Figure 17-10. Clock Synchronization
A high to low transition on the SCL line will force the line low for all masters on the bus and they start timing their
low clock period. The timing length of the low clock period can vary between the masters. When a master
(DEVICE1 in this case) has completed its low period it releases the SCL line. However, the SCL line will not go
high before all masters have released it. Consequently the SCL line will be held low by the device with the longest
low period (DEVICE2). Devices with shorter low periods must insert a wait-state until the clock is released. All mas-
ters start their high period when the SCL line is released by all devices and has become high. The device which
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