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參數(shù)資料
| 型號(hào)： | MQ83C154XXX-16/883D |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 16 MHz, MICROCONTROLLER, CQFP44 |
| 文件頁數(shù)： | 184/204頁 |
| 文件大?。?/td> | 5687K |
| 代理商： | MQ83C154XXX-16/883D |
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80
ATtiny40 [DATASHEET]
8263B–AVR–01/2013
clock as the TCNT1 value is copied into Input Capture Register. If enabled (ICIE1=1), the Input Capture Flag gen-
erates an Input Capture interrupt. The ICF1 flag is automatically cleared when the interrupt is executed.
Alternatively the ICF1 flag can be cleared by software by writing a logical one to its I/O bit location.
12.5.1
Input Capture Trigger Source
The trigger source for the Input Capture unit is the Input Capture pin (ICP1).
The Input Capture pin (ICP1) input is sampled using the same technique as for the T1 pin (Figure 12-4 on page
88). The edge detector is also identical. However, when the noise canceler is enabled, additional logic is inserted
before the edge detector, which increases the delay by four system clock cycles. An Input Capture can also be trig-
gered by software by controlling the port of the ICP1 pin.
12.5.2
Noise Canceler
The noise canceler improves noise immunity by using a simple digital filtering scheme. The noise canceler input is
monitored over four samples, and all four must be equal for changing the output that in turn is used by the edge
detector.
The noise canceler is enabled by setting the Input Capture Noise Canceler (ICNC1) bit in Timer/Counter Control
Register A (TCCR1A). When enabled the noise canceler introduces additional four system clock cycles of delay
from a change applied to the input, to the update of the ICR1 Register. The noise canceler uses the system clock
and is therefore not affected by the prescaler.
12.5.3
Using the Input Capture Unit
The main challenge when using the Input Capture unit is to assign enough processor capacity for handling the
incoming events. The time between two events is critical. If the processor has not read the captured value in the
ICR1 Register before the next event occurs, the ICR1 will be overwritten with a new value. In this case the result of
the capture will be incorrect.
When using the Input Capture interrupt, the ICR1 Register should be read as early in the interrupt handler routine
as possible. The maximum interrupt response time is dependent on the maximum number of clock cycles it takes
to handle any of the other interrupt requests.
Measurement of an external signal’s duty cycle requires that the trigger edge is changed after each capture.
Changing the edge sensing must be done as early as possible after the ICR1 Register has been read. After a
change of the edge, the Input Capture Flag (ICF1) must be cleared by software (writing a logical one to the I/O bit
location). For measuring frequency only, the trigger edge change is not required (if an interrupt handler is used).
12.6
Output Compare Unit
The comparator continuously compares Timer/Counter (TCNT1) with the Output Compare Registers (OCR1A and
OCR1B), and whenever the Timer/Counter equals to the Output Compare Regisers, the comparator signals a
match. A match will set the Output Compare Flag at the next timer clock cycle. In 8-bit mode the match can set
either the Output Compare Flag OCF1A or OCF1B, but in 16-bit mode the match can set only the Output Compare
Flag OCF1A as there is only one Output Compare Unit. If the corresponding interrupt is enabled, the Output Com-
pare Flag generates an Output Compare interrupt. The Output Compare Flag is automatically cleared when the
interrupt is executed. Alternatively, the flag can be cleared by software by writing a logical one to its I/O bit location.
Figure 12-3 shows a block diagram of the Output Compare unit.
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