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參數(shù)資料
| 型號(hào)： | MQ83C154XXX-16/883D |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 16 MHz, MICROCONTROLLER, CQFP44 |
| 文件頁(yè)數(shù)： | 124/204頁(yè) |
| 文件大小： | 5687K |
| 代理商： | MQ83C154XXX-16/883D |
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26
ATtiny40 [DATASHEET]
8263B–AVR–01/2013
7.4.5
Port Pins
When entering a sleep mode, all port pins should be configured to use minimum power. The most important thing
is then to ensure that no pins drive resistive loads. In sleep modes where the I/O clock (clk
I/O) is stopped, the input
buffers of the device will be disabled. This ensures that no power is consumed by the input logic when not needed.
In some cases, the input logic is needed for detecting wake-up conditions, and it will then be enabled. Refer to the
section “Digital Input Enable and Sleep Modes” on page 46 for details on which pins are enabled. If the input buffer
is enabled and the input signal is left floating or has an analog signal level close to V
CC/2, the input buffer will use
excessive power.
For analog input pins, the digital input buffer should be disabled at all times. An analog signal level close to V
CC/2
on an input pin can cause significant current even in active mode. Digital input buffers can be disabled by writing to
the Digital Input Disable Register (DIDR0). Refer to “DIDR0 – Digital Input Disable Register 0” on page 97 for
details.
7.5
Register Description
7.5.1
MCUCR – MCU Control Register
The MCU Control Register contains bits for controlling external interrupt sensing and power management.
Bit 5 – Res: Reserved Bit
This bit is reserved and will always read as zero.
Bit 4 – BODS: BOD Sleep
In order to disable BOD during sleep (see Table 7-1 on page 23) the BODS bit must be written to logic one. This is
controlled by a protected change sequence, as follows:
1.
Write the signature for change enable of protected I/O registers to register CCP.
2.
Within four instruction cycles write the BODS bit.
A sleep instruction must be executed while BODS is active in order to turn off the BOD for the actual sleep mode.
The BODS bit is automatically cleared when the device wakes up. Alternatively the BODS bit can be cleared by
writing logic zero to it. This does not require protected sequence.
Bits 3:1 – SM[2:0]: Sleep Mode Select Bits 2, 1 and 0
These bits select between available sleep modes, as shown in Table 7-2.
Bit
765
432
1
0
ISC01
ISC00
–
BODS
SM2
SM1
SM0
SE
MCUCR
Read/Write
R/W
R
R/W
Initial Value
0
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