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ATtiny40 [DATASHEET]
8263B–AVR–01/2013
The most typical and general setup for interrupt vector addresses in ATtiny40 is shown in the program example
below.
Note:
9.2
External Interrupts
External Interrupts are triggered by the INT0 pin or any of the PCINT[17:0] pins. Observe that, if enabled, the inter-
rupts will trigger even if the INT0 or PCINT[17:0] pins are configured as outputs. This feature provides a way of
generating a software interrupt.
Pin change 0 interrupts PCI0 will trigger if any enabled PCINT[7:0] pin toggles. Pin change 1 interrupts PCI1 will
trigger if any enabled PCINT[11:8] pin toggles. Pin change 2 interrupts PCI1 will trigger if any enabled
PCINT[17:12] pin toggles. The PCMSK0, PCMSK1 and PCMSK2 Registers control which pins contribute to the pin
change interrupts. Pin change interrupts on PCINT[17:0] are detected asynchronously, which means that these
interrupts can be used for waking the part also from sleep modes other than Idle mode.
The INT0 interrupt can be triggered by a falling or rising edge or a low level. This is set up as shown in
“MCUCR –rupt will trigger as long as the pin is held low. Note that recognition of falling or rising edge interrupts on INT0
Assembly Code Example
.org 0x0000
;Set address of next statement
rjmp RESET
; Address 0x0000
rjmp INT0_ISR
; Address 0x0001
rjmp PCINT0_ISR
; Address 0x0002
rjmp PCINT1_ISR
; Address 0x0003
rjmp PCINT2_ISR
; Address 0x0004
rjmp WDT_ISR
; Address 0x0005
rjmp TIM1_CAPT_ISR
; Address 0x0006
rjmp TIM1_COMPA_ISR
; Address 0x0007
rjmp TIM1_COMPB_ISR
; Address 0x0008
rjmp TIM1_OVF_ISR
; Address 0x0009
rjmp TIM0_COMPA_ISR
; Address 0x000A
rjmp TIM0_COMPB_ISR
; Address 0x000B
rjmp TIM0_OVF_ISR
; Address 0x000C
rjmp ANA_COMP_ISR
; Address 0x000D
rjmp ADC_ISR
; Address 0x000E
rjmp TWI_SLAVE_ISR
; Address 0x000F
rjmp SPI_ISR
; Address 0x0010
rjmp QTRIP_ISR
; Address 0x0011
RESET:
; Main program start
<instr>
; Address 0x0012
...