
112
ATtiny40 [DATASHEET]
8263B–AVR–01/2013
ADSC will read as one as long as a conversion is in progress. When the conversion is complete, it returns to zero.
Writing zero to this bit has no effect.
Bit 5 – ADATE: ADC Auto Trigger Enable
When this bit is written to one, Auto Triggering of the ADC is enabled. The ADC will start a conversion on a positive
edge of the selected trigger signal. The trigger source is selected by setting the ADC Trigger Select bits, ADTS in
ADCSRB.
Bit 4 – ADIF: ADC Interrupt Flag
This bit is set when an ADC conversion completes and the data registers are updated. The ADC Conversion Com-
plete Interrupt is executed if the ADIE bit and the I-bit in SREG are set. ADIF is cleared by hardware when
executing the corresponding interrupt handling vector. Alternatively, ADIF is cleared by writing a logical one to the
flag.
Beware that if doing a Read-Modify-Write on ADCSRA, a pending interrupt can be disabled.
Bit 3 – ADIE: ADC Interrupt Enable
When this bit is written to one and the I-bit in SREG is set, the ADC Conversion Complete Interrupt is activated.
Bits 2:0 – ADPS[2:0]: ADC Prescaler Select Bits
These bits determine the division factor between the system clock frequency and the input clock to the ADC.
15.13.4
ADCSRB – ADC Control and Status Register B
Bit 7 – VDEN
This bit is reserved for QTouch, always write as zero.
Bit 6 – VDPD
This bit is reserved for QTouch, always write as zero.
Bits 5:4 – Res: Reserved Bits
These are reserved bits. For compatibility with future devices always write these bits to zero.
Table 15-5.
ADC Prescaler Selections
ADPS2
ADPS1
ADPS0
Division Factor
000
2
001
2
010
4
011
8
100
16
101
32
110
64
111
128
Bit
7
6543
210
VDEN
VDPD
–
ADLAR
ADTS2
ADTS1
ADTS0
ADCSRB
Read/Write
R/W
R
R/W
Initial Value
0
0000
000