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參數(shù)資料
| 型號(hào)： | MPC9894 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Quad Input Redundant IDCS Clock Generator |
| 中文描述： | 四路輸入冗余IDC機(jī)房，時(shí)鐘發(fā)生器 |
| 文件頁數(shù)： | 7/28頁 |
| 文件大?。?/td> | 367K |
| 代理商： | MPC9894 |
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Advanced Clock Drivers Devices
Freescale Semiconductor
7
MPC9894
The SEL_STAT[1:0] pins indicate which of the four input
clocks is the current reference clock. In the automatic mode
and In the case of the reference clock failure, the SEL_STAT
flag will indicate a reference clock different from the original
primary clock selected by IDCS_MODE[2:0]. The CLK_STAT
outputs are mirrored in register 5, bits 1:0 for I
2
C bus access.
If all four clock inputs are not qualified the VCO will slew to
its lowest frequency. This condition will be indicated by the
LOCK pin being de-asserted. The MPC9894 will remain in
this state until an input clock is restored and the device is
reset via the MR pin.
Clock Failure Detection
The MPC9894 clock failure detection is performed using
an input clock amplitude check combined with an activity
detector. The following conditions will trigger a failed clock
status (CLK_STATn = 0) on any qualified clock
(CLK_VALIDn = 1). These conditions are:
1.
Either or both CLKx, CLKx are disconnected from the
input clock source and open.
2.
CLKx and CLKx are shorted together
3.
Either or both CLKx or CLKx are shorted to GND
4.
Both CLKx and CLKx are shorted to a power supply
5.
Amplitude of CLKx or CLKx is less than V
PP, OK
(refer to
AC specification,
Table 39
)
In addition, the currently selected clock is checked by a
phase-frequency detector after the input divider (P). This is
triggered by a phase step of mae
(
)
. This phase detector will
issue a failed clock status (CLK_STATn = 0) within 'P' clock
cycles.
The IDCS does not detect changes of the reference
frequency or the reference frequency being out of the
specified input frequency range. This includes errors such as
reference frequency drift due to crystal aging etc.
Clearing of IDCS Alarm Flags
The input clock status flags are set by a clock failure and
remain set until manually cleared (sticky). Clearing can be
done by either of two methods. All status flags can be cleared
by the package pin, CLK_ALARM_RST. Or individual status
flags can be cleared via register bits, ALARM_RST[3:0]. The
CLK_ALARM_RST pin is activated by a negative edge on the
pin. This clears all CLK_STAT[3:0] flags and returns the IDCS
to the primary clock source. The SEL_STAT[1:0]-selected
clock indicator now reflects the IDCS_MODE[2:0] setting.
By using ALARM_RST[3:0] (register 2) individual
CLK_STAT[3:0] bits are cleared by writing a logic 0 to the
individual bit in this register. It is important to note that this
action does not return the IDCS to the primary clock.
Table 4. Input Clock Qualifier and Status Flag
Input Clock
Associated Input Qualifier
(1)
1. The input qualifier logic can be enabled or disabled by setting the QUAL_EN bit in register 3.
Associated Input Clock Status Flag
Pin
Register location
CLK0
CLK_VALID0
CLK_STAT0
Device register 5, bit 3
CLK1
CLK_VALID1
CLK_STAT1
Device register 5, bit 4
CLK2
CLK_VALID2
CLK_STAT2
Device register 5, bit 5
CLK3
CLK_VALID3
CLK_STAT3
Device register 5, bit 6
Table 5. Input Clock Status CLK_STAT[3:0]
CLK_STAT[]
Description
0
Clock input failure
1
Clock input signal valid
Table 6. Clock Input Qualifier CLK_VALID[3:0]
CLK_VALID[]
Associated Input Clock
0
Not qualified and will not be selected
1
Qualified
Table 7. SEL_STAT[1:0]
SEL_STAT[1:0]
Selected clock input
00
CLK0
01
CLK1
10
CLK2
11
CLK3
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