
Advanced Clock Drivers Devices
Freescale Semiconductor
21
MPC9894
V
DD
= 3.3 V ±5%, V
DDAB,CD,IC
= 3.3 V ±5% or V
DDAB,CD,IC
= 2.5 V ±5%
MR
and PLL Lock
t
LOCK
Maximum PLL Lock Time
10
μ
s
t
reset_ref
MR
hold time on power up
2
ps
t
reset_pulse
MR
hold time
100
ns
1. AC characteristics are design targets and pending characterization.
2. AC characteristics apply for parallel output termination of 50
to V
TT
.
3. In bypass mode, the MPC9894 divides the input reference clock.
4. The input reference frequency must match the VCO lock range divided by the total feedback divider ratio: f
REF
= (f
VCO
÷
M)
N.
5. All Input Clock frequencies must be within this value to guarantee smooth phase transition on input clock switch.
6. V
PP
is the minimum differential input voltage swing required to maintain AC characteristics including tpd and device-to-device skew.
7. V
PP
,
OK
is the minimum differential input voltage swing required for a valid clock signal. Above V
PP, OK
the input will be detected as a good
clock (see IDCS).
8. V
PP
,
NOK
is the maximum differential input voltage swing for a guaranteed bad clock. Below V
PP, NOK
the input will be detected as a failed
clock (see IDCS).
9. V
DDAB
= V
DDCD
10. Rate of period change is the maximum change of the clock output signal period T per cycle on a IDCS commanded switch.
11. Rate of period change is the maximum change of the clock output signal period T per cycle on a IDCS commanded switch.
12. –3 dB point of PLL transfer characteristics.
Table 39. AC Characteristics (T
J
= –40°C to +110°C)
(1) (2)
(Continued)
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
Z = 50
RT = 50
V
TT
DUT MPC9894
Z = 50
Differential
Pulse Generator
Z = 50
RT = 50
V
TT
Figure 7. MPC9894 AC Test Reference (Media = 0)
Figure 8 . MPC9894 AC Test Reference (Media = 1)
Z = 50
RT = 100
DUT MPC9894
Z = 50
Differential
Pulse Generator
Z = 50
RT = 50
V
TT