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參數(shù)資料
| 型號： | MPC9894 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Quad Input Redundant IDCS Clock Generator |
| 中文描述： | 四路輸入冗余IDC機(jī)房，時鐘發(fā)生器 |
| 文件頁數(shù)： | 22/28頁 |
| 文件大?。?/td> | 367K |
| 代理商： | MPC9894 |
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Advanced Clock Drivers Devices
Freescale Semiconductor
22
MPC9894
MPC9894 Pin and Package
Table 40. MPC9894 Pin Listing
Signal Name
Description
Direction
Type
Active State
Supply
Pin
CLK0
Clock0 Positive Input
Input
LVPECL
—
V
DDIC
D1
CLK0
Clock0 Negative Input
Input
LVPECL
—
V
DDIC
D2
CLK1
Clock1 Positive Input
Input
LVPECL
—
V
DDIC
E3
CLK1
Clock1 Negative Input
Input
LVPECL
—
V
DDIC
E2
CLK2
Clock2 Positive Input
Input
LVPECL
—
V
DDIC
F3
CLK2
Clock2 Negative Input
Input
LVPECL
—
V
DDIC
F2
CLK3
Clock3 Positive Input
Input
LVPECL
—
V
DDIC
G1
CLK3
Clock3 Negative Input
Input
LVPECL
—
V
DDIC
G2
FB_IN
Feedback Clock Positive Input
Input
LVPECL
—
V
DDIC
C1
FB_IN
Feedback Clock Negative Input
Input
LVPECL
—
V
DDIC
C2
QA0
Positive Differential Clock Output
Output
LVPECL
—
V
DDAB
K4
QA0
Negative Differential Clock Output
Output
LVPECL
—
V
DDAB
J4
QA1
Positive Differential Clock Output
Output
LVPECL
—
V
DDAB
K5
QA1
Negative Differential Clock Output
Output
LVPECL
—
V
DDAB
J5
QB0
Positive Differential Clock Output
Output
LVPECL
—
V
DDAB
K7
QB0
Negative Differential Clock Output
Output
LVPECL
—
V
DDAB
J7
QB1
Positive Differential Clock Output
Output
LVPECL
—
V
DDAB
K6
QB1
Negative Differential Clock Output
Output
LVPECL
—
V
DDAB
J6
QC0
Positive Differential Clock Output
Output
LVPECL
—
V
DDCD
A7
QC0
Negative Differential Clock Output
Output
LVPECL
—
V
DDCD
B7
QC1
Positive Differential Clock Output
Output
LVPECL
—
V
DDCD
A6
QC1
Negative Differential Clock Output
Output
LVPECL
—
V
DDCD
B6
QD0
Positive Differential Clock Output
Output
LVPECL
—
V
DDCD
A4
QD0
Negative Differential Clock Output
Output
LVPECL
—
V
DDCD
B4
QD1
Positive Differential Clock Output
Output
LVPECL
—
V
DDCD
A5
QD1
Negative Differential Clock Output
Output
LVPECL
—
V
DDCD
B5
QFB
Positive Differential Clock Output
Output
LVPECL
—
V
DDCD
A3
QFB
Negative Differential Clock Output
Output
LVPECL
—
V
DDCD
B3
CLK_VALID3
Qualifier for clock input CLK3
Input
LVCMOS
High
V
DD
F10
CLK_VALID2
Qualifier for clock input CLK2
Input
LVCMOS
High
V
DD
E10
CLK_VALID1
Qualifier for clock input CLK1
Input
LVCMOS
High
V
DD
E9
CLK_VALID0
Qualifier for clock input CLK0
Input
LVCMOS
High
V
DD
E8
CLK_ALARM_RST Reset of all four alarm status flags and clock
selection status flag
Input
LVCMOS
Low
V
DD
F8
PLL_BYPASS
Select PLL of static test mode
Input
LVCMOS
High
V
DD
F9
MEDIA
Output impedance control (high = 50
)
I
2
C Interface Control, Clock
I
2
C Interface Control, Data
I
2
C Interface Control, Address 2 (MSB)
I
2
C Interface Control, Address 1
I
2
C Interface Control, Address 1 (LSB)
Input
LVCMOS
High
V
DD
E7
SCL
I/O
LVCMOS
—
V
DD
C9
SDA
I/O
LVCMOS
—
V
DD
C10
ADDR2
Input
LVCMOS
—
V
DD
A9
ADDR1
Input
LVCMOS
—
V
DD
B8
ADDR0
Input
LVCMOS
—
V
DD
A8
MR
Device Master Reset
Input
LVCMOS
Low
V
DD
D10
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